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copyright ? cirrus logic, inc. 2005 (all rights reserved) http://www.cirrus.com advance product information this document contains information for a new product. cirrus logic reserves the right to modify this product without notice. september '05 ds679a2 low power, stereo codec with headphone amp digital to analog features ! 98 db dynamic range (a-wtd) ! -86 db thd+n ! headphone amplifier - gnd centered ? on-chip charge pump provides -va_hp ? no dc-blocking capacitor required ? 46 mw power into stereo 16 ? @ 1.8 v ? 88 mw power into stereo 16 ? @ 2.5 v ? -75 db thd+n ! digital signal processing engine ? bass & treble tone control, de-emphasis ? pcm + adc mix w/independent vol control ? master digital volume control ? soft ramp & zero cross transitions ! beep generator ? tone selections across two octaves ? separate volume control ? programmable on & off time intervals ? continuous, periodic or one-shot beep selections ! programmable peak-d etect and limiter ! pop and click suppression analog to digital features ! 98 db dynamic range (a-wtd) ! -88 db thd+n ! analog gain controls ? +32 db or +16 db mic pre-amplifiers ? analog programmable gain amplifier (pga) ! +20 db digital boost ! programmable automatic level control (alc) ? noise gate for noise suppression ? programmable threshold and attack/release rates ! independent channel control ! digital volume control ! high-pass filter disable for dc measurements ! stereo 3:1 analog input mux ! dual mic inputs ? programmable, low noise mic bias levels ? differential mic mix for common mode noise rejection ! very low 64 fs oversampling clock reduces power consumption 1.8 v to 3.3 v multibit ? modulator charge pump left hp out right hp out multibit oversampling adc multibit oversampling adc serial audio input serial audio output 1.8 v to 2.5 v 1.8 v to 2.5 v mux pga pcm serial interface register configuration level translator reset hardware mode or i 2 c & spi software mode control data stereo input 1 stereo input 2 stereo input 3 / mic input 1 & 2 pga +32 db +32 db volume controls beep generator mux mux headphone amp - gnd centered headphone amp - gnd centered alc mic bias 1.8 v to 2.5 v mux mux switched capacitor dac and filter switched capacitor dac and filter high pass filters alc digital signal processing engine cs42l51
2 ds679a2 cs42l51 system features ! 24-bit converters ! 4 khz to 96 khz sample rate ! multi-bit delta sigma architecture ! low power operation ? stereo playback: 12.93 mw @ 1.8 v ? stereo record and playback: 20.18 mw @ 1.8 v ! variable power supplies ? 1.8 v to 2.5 v digital & analog ? 1.8 v to 3.3 v interface logic ! power down management ? adc, dac, codec, mic pre-amplifier, pga ! software mode (i2c & spi ? control) ! hardware mode (stand-alone control) ! digital routing/mixes: ? analog out = adc + digital in ? digital out = adc + digital in ? internal digital loopback ? mono mixes ! flexible clocking options ? master or slave operation ? high-impedance digital output option (for easy muxing between codec and other data sources) ? quarter-speed mode - (i.e. allows 8 khz fs while maintaining a flat noise floor up to 16 khz) applications ! hdd & flash-based portable audio players ! md players/recorders ! pdas ! personal media players ! portable game consoles ! digital voice recorders ! digital camcorders ! digital cameras ! smart phones general description the cs42l51 is a highly integrated, 24-bit, 96 khz, low power stereo codec. based on multi-bit, delta-sigma modulation, it allows infinite sample rate adjustment be- tween 4 khz and 96 khz. both the adc and dac offer many features suitable for low power, portable system applications. the adc input path allows independent channel control of a number of features. an input multiplexer selects be- tween line-level or microphone level inputs for each channel. the microphone input path includes a select- able programmable-gain pre-amplifier stage and a low noise mic bias voltage supply. a pga is available for line or microphone inputs and provides analog gain with soft ramp and zero cross transitions. the adc also fea- tures a digital volume attenuator with soft ramp transitions. a programmable alc and noise gate mon- itor the input signals and adjust the volume levels appropriately. the dac output path includes a digital signal process- ing engine. tone control provides bass and treble adjustment of four selectable corner frequencies. the mixer allows independent volume control for both the adc mix and the pcm mix, as well as a master digital volume control for the analog output. all volume level changes may be configured to occur on soft ramp and zero cross transitions. the dac also includes de-em- phasis, limiting functions and a beep generator delivering tones selectable across a range of two full octaves. the stereo headphone amplifier is powered from a sep- arate positive supply and the integrated charge pump provides a negative supply. this allows a ground-cen- tered analog output with a wide signal swing and eliminates external dc-blocking capacitors. in addition to its many features, the cs42l51 operates from a low-voltage analog and digital core, making this codec ideal for portable systems that require ex- tremely low power consumption in a minimal amount of space. the cs42l51 is available in a 32-pin qfn package in both commercial (-10 to +70 c) and automotive grades (-40 to +85 c). the cdb42l51 customer dem- onstration board is also available for device evaluation and implementation suggestions. please see ?ordering information? on page 81 for complete details.
ds679a2 3 cs42l51 table of contents 1. pin descriptions - software (hardware) mode .................................................... 7 1.1 digital i/o pin characteristics ........................................................................................... .9 2. typical connection diagrams ................................................................................... 10 3. characteristic and specification tabl es ........................................................... 12 specified operating conditions . .............. ................ ............. ............. ............. ......... 12 absolute maximum ratings ...... ................ ................ ................ ............. ............. ......... 12 analog input characteristics (commercial - cnz)............................................ 13 analog input characteristics (automotive - dnz) ............................................ 14 adc digital filter characteristics......................................................................... 15 analog output characteristics (commercial - cnz)........................................ 16 analog output characteristics (automot ive - dnz) ........................................ 17 line output voltage characteristics ................................................................... 18 headphone output power characteristics........................................................ 19 combined dac interpolation & on-chip analog filter response................ 20 switching specifications - serial port ................................................................. 20 switching specifications - i2c control port....................................................... 22 switching characteristics - spi control port.................................................. 23 dc electrical characteristics ................................................................................ 24 digital interface specifications & characteristics ....................................... 24 power consumption ...................................................................................................... 25 4. applications .............................................................................................................. ....... 26 4.1 overview .................................................................................................................. ........ 26 4.1.1 architecture ......................................................................................................... 26 4.1.2 line & mic inputs ............................................................................................... 26 4.1.3 line & headphone outputs ................................................................................. 26 4.1.4 signal processing engine ................................................................................... 26 4.1.5 beep generator .................................................................................................. 26 4.1.6 device control (hardwar e or software mode) .................................................... 26 4.1.7 power management ............................................................................................ 26 4.2 hardware mode ............................................................................................................. .. 27 4.3 analog inputs ............................................................................................................ ...... 28 4.3.1 digital code, offset & dc measuremen t ............................................................ 28 4.3.2 high-pass filter and dc offset calibra tion ........................................................ 29 4.3.3 digital routing ..................................................................................................... 29 4.3.4 differential inputs ................................................................................................ 29 4.3.4.1 external passive co mponents ................................................................ 29 4.3.5 analog input multiplexer ..................................................................................... 30 4.3.6 mic & pga gain ................................................................................................. 31 4.3.7 automatic level control (alc) ........................................................................... 31 4.3.8 noise gate .......................................................................................................... 32 4.4 analog outputs ............................................................................................................ .... 33 4.4.1 de-emphasis filter ............................................................................................. 33 4.4.2 volume controls ................................................................................................. 34 4.4.3 mono channel mixer ........................................................................................... 34 4.4.4 beep generator .................................................................................................. 34 4.4.5 tone control ....................................................................................................... 35 4.4.6 limiter ................................................................................................................. 35 4.4.7 line-level outputs and filtering ......................................................................... 36 4.4.8 on-chip charge pump ....................................................................................... 36 4.5 serial port clocking ...................................................................................................... ... 37 4.5.1 slave ................................................................................................................... 37 4.5.2 master ................................................................................................................. 3 8
4 ds679a2 cs42l51 4.5.3 high-impedance digital output ........................................................................... 38 4.5.4 quarter- and half-speed mode ........................................................................... 39 4.6 digital interface formats ................................................................................................. 39 4.7 initialization ............................................................................................................ .......... 40 4.8 recommended power-up sequence .............................................................................. 40 4.9 recommended power-down sequence ......................................................................... 41 4.10 software mode ............................................................................................................ .. 42 4.10.1 spi control ........................................................................................................ 42 4.10.2 i2c control ......................................................................................................... 42 4.10.3 memory address pointer (map) ....... ................................................................ 44 4.10.3.1 map increment (incr) .......................................................................... 44 5. register quick reference .......................................................................................... 45 6. register description .................................................................................................... 47 6.1 chip i.d. and revision register (address 01h) (read only) ........................................... 47 6.2 power control 1 (address 02h) ....................................................................................... 47 6.3 mic power control & speed control (addre ss 03h) ...................................................... 48 6.4 interface control (address 04 h) ...................................................................................... 49 6.5 mic control (address 05h) .............................................................................................. 51 6.6 adc control (address 06h) ............................................................................................. 52 6.7 adcx input select, invert & mute (address 07h) ............................................................ 53 6.8 dac output control (address 08h) ................................................................................. 54 6.9 dac control (address 09h) ............................................................................................. 55 6.10 alcx & pgax control: alca, pgaa (address 0ah) & alcb, pgab (address 0bh) ..................................... 56 6.11 adcx attenuator: adca (address 0ch) & adcb (address 0dh) ............................................................ 57 6.12 adcx mixer volume control: adca (address 0eh) & adcb (address 0fh) ............................................................. 58 6.13 pcmx mixer volume control: pcma (address 10h) & pcmb (address 11h) ............................................................. 59 6.14 beep frequency & timing configuration (address 12h) ............................................... 60 6.15 beep off time & volume (address 13h) ....................................................................... 61 6.16 beep configurat ion & tone configuration (address 14h) ............................................. 62 6.17 tone control (address 15h) .......................................................................................... 63 6.18 aoutx volume control: aouta (address 16h) & aoutb (address 17h) ......................................................... 64 6.20 limiter threshold szc disable (address 1 9h) .............................................................. 65 6.21 limiter release rate register (address 1a h) ............................................................... 66 6.22 limiter attack rate register (address 1b h) .................................................................. 67 6.23 alc enable & attack rate (address 1ch) .................................................................... 67 6.24 alc release rate (address 1dh) ................................................................................. 68 6.25 alc threshold (address 1eh) ....................................................................................... 69 6.26 noise gate configuration & misc. (address 1fh) .......................................................... 70 6.27 status (address 20h) (read only) ................................................................................ 71 6.28 charge pump frequency (a ddress 21h) ....................................................................... 71 7. analog performance plots ...................................................................................... 72 7.1 headphone thd+n versus output power pl ots ............................................................. 72 7.2 adc_filt+ capacitor effects on thd+n ....................................................................... 74 8. example system clock frequencies ...................................................................... 75 8.1 auto detect enabled ........ ............................................................................................... .75 8.2 auto detect disabled ................................. ..................................................................... .76 9. pcb layout considerations ....................................................................................... 77 9.1 power supply, grounding ................................................................................................ 77 9.2 qfn thermal pad ........................................................................................................... 77
ds679a2 5 cs42l51 10. adc & dac digital filters .......................................................................................... 78 11. parameter definitions ................................................................................................ 79 12. package dimensions ................................................................................................... 80 thermal characteristics............................................................................................ 80 13. ordering information ............................................................................................... 81 14. references ............................................................................................................... ....... 81 15. revision history ........................................................................................................ ... 82
6 ds679a2 cs42l51 list of figures figure 1. typical connection diagram (software mo de) .......................................................................... 10 figure 2. typical connection diagram (hardware mode)......................................................................... 1 1 figure 3. headphone output test load........................................................................................... ......... 19 figure 4. serial audio interface slave mode timing............................................................................. .... 21 figure 5. tdm serial audio interface timing .................................................................................... ........ 21 figure 6. serial audio interface master mode timi ng............................................................................ ... 21 figure 7. control port timing - i2c ................ ............................................................................ ................ 22 figure 8. control port timing - spi format......... ............................................................................ .......... 23 figure 9. analog input architecture............................................................................................ ............... 28 figure 10. mic input mix w/common mode rejection.............................................................................. 30 figure 11. differential input........................... ....................................................................... ..................... 30 figure 12. alc ................................................................................................................. ......................... 31 figure 13. noise gate attenuation.............................................................................................. .............. 32 figure 14. output architecture ................................................................................................. ................. 33 figure 15. de-emphasis curve................................................................................................... .............. 33 figure 16. beep configuration options.......................................................................................... ........... 34 figure 17. peak detect & limiter ............................................................................................... ............... 35 figure 18. master mode timing .................................................................................................. .............. 38 figure 19. tri-state serial port ............................................................................................... .................. 38 figure 20. i2s format .......................................................................................................... ...................... 39 figure 21. left-justified format ............................................................................................... ................. 39 figure 22. right-justified format (dac only) ................................................................................... ........ 39 figure 23. initialization flow chart........................................................................................... ................. 41 figure 24. control port timing in spi mode ..................................................................................... ........ 42 figure 25. control port timing, i2c write...................................................................................... ............ 43 figure 26. control port timing, i2c read....................................................................................... ........... 43 figure 27. ain & pga selection ................................................................................................. .............. 53 figure 28. thd+n vs. ouput power per channel at 1.8 v (16 ? load) .................................................... 72 figure 29. thd+n vs. ouput power per channel at 2.5 v (16 ? load) .................................................... 72 figure 30. thd+n vs. ouput power per channel at 1.8 v (32 ? load) .................................................... 73 figure 31. thd+n vs. ouput power per channel at 2.5 v (32 ? load) .................................................... 73 figure 32. adc thd+n vs. frequency w/capacitor effects..................................................................... 74 figure 33. adc passband ripple ................................................................................................. ............ 78 figure 34. adc stopband rejection .............................................................................................. ........... 78 figure 35. dac passband ripple ................................................................................................. ............ 78 figure 36. dac stopband ........................................................................................................ ................. 78 figure 35. dac transition band ................................................................................................. .............. 78 figure 36. dac transition band (detail)........................................................................................ ........... 78 figure 35. adc transition band ................................................................................................. .............. 78 figure 36. adc transition band (detail)........................................................................................ ........... 78
ds679a2 7 cs42l51 1. pin descriptions - so ftware (hardware) mode pin name # pin description lrck 1 left right clock (input/output ) - determines which channel, left or right, is currently active on the serial audio data line. sda/cdin 2 serial control data ( input / output ) - sda is a data i/o in i2c mode. cdin is the input data line for the control port interface in spi mode. (mclkdiv2) mclk divide by 2 ( input ) - hardware mode: divides the mclk by 2 prior to all internal circuitry. scl/cclk 3 serial control port clock ( input ) - serial clock for th e serial control port. (i2s/lj ) interface format selection ( input ) - hardware mode: selects between i2s & left-justified interface for- mats for the adc & dac. ad0/cs 4 address bit 0 (i2c) / control port chip select (spi) (input) - ad0 is a chip address pin in i2c mode; cs is the chip select signal for spi format. (dem) de-emphasis (input) - hardware mode: enables/disables the de-emphasis filter. va_hp 5 analog power for headphone (input) - positive power for the internal analog headphone section. flyp 6 charge pump cap positive node (input) - positive node for the external charge pump capacitor. gndhp 7 analog ground ( input ) - ground reference for the internal headphone/charge pump section. flyn 8 charge pump cap negative node (input) - negative node for the external charge pump capacitor. vss_hp 9 negative voltage from charge pump (output) - negative voltage rail for the internal analog head- phone section. aoutb aouta 10 11 analog audio output ( output ) - the full-scale output level is specified in the dac analog characteris- tics specification table. va 12 analog power (input) - positive power for the internal analog section. agnd 13 analog ground ( input ) - ground reference for the internal analog section. 10 9 8 7 6 5 4 3 2 1 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 cs42l51 vd dgnd sdout (m/s ) mclk sdin sclk vss_hp aoutb aouta va agnd dac_filt+ adc_filt+ vq sda/cdin (mclkdiv2) scl/cclk (i2s/lj ) ad0/cs (dem) flyp vl reset gndhp flyn afilta ain1a ain1b ain2a ain2b/bias micin1/ain3a micin2/bias/ain3b afiltb va_hp lrck
8 ds679a2 cs42l51 dac_filt+ adc_filt+ 14 16 positive voltage reference ( output ) - positive reference voltage for the internal sampling circuits. vq 15 quiescent voltage ( output ) - filter connection for internal quiescent voltage. micin1/ ain3a 17 microphone input 1 ( input ) - the full-scale level is specified in th e adc analog characteristics specifi- cation table. micin2/ bias/ain3b 18 microphone input 2 ( input/output ) - the full-scale level is specified in the adc analog characteristics specification table. this pin can al so be configured as an output to pr ovide a low noise bias supply for an external microphone. electrical characteristics are sp ecified in the dc electrical characteristics table. ain2a 19 analog input ( input ) - the full-scale level is specified in the adc analog characteristics specification table. ain2b/bias 20 analog input ( input/output ) - the full-scale level is specified in th e adc analog characteristics specifi- cation table. this pin can also be configured as an output to provide a low noise bias supply for an exter- nal microphone. electrical characteristics are spec ified in the dc electrical characteristics table. afilta afiltb 21 22 filter connection ( output ) - filter connection for the adc inputs. ain1a ain1b 23 24 analog input ( input ) - the full-scale level is specified in the adc analog characteristics specification table. reset 25 reset ( input ) - the device enters a low power mode when this pin is driven low. vl 26 digital interface power ( input ) - determines the required signal level for the serial audio interface and host control port. refer to the recommended op erating conditions for appropriate voltages. vd 27 digital power ( input ) - positive power for the internal digital section. dgnd 28 digital ground ( input ) - ground reference for the internal digital section. sdout 29 serial audio data output ( output ) - output for two?s complement serial audio data. (m/s ) serial port master/slave ( input/output ) - hardware mode startup option: selects between master and slave mode for the serial port. mclk 30 master clock ( input ) -clock source for the delta-sigma modulators. sclk 31 serial clock (input/output ) - serial clock for the serial audio interface. sdin 32 serial audio data input ( input ) - input for two?s complement serial audio data. thermal pad - thermal relief pad for optimized heat dissipation. see ?qfn thermal pad? on page 77 .
ds679a2 9 cs42l51 1.1 digital i/o pin characteristics the logic level for each input should adhere to the corr esponding power rail and should not exceed the maximum ratings. power rail pin name sw/(hw) i/o driver receiver vl reset input - 1.8 v - 3.3 v scl/cclk (i2s/lj ) input - 1.8 v - 3.3 v, with hysteresis sda/cdin (mclkdiv2) input/output 1.8 v - 3.3 v, cmos/open drain 1.8 v - 3.3 v, with hysteresis ad0/cs (dem) input - 1.8 v - 3.3 v mclk input - 1.8 v - 3.3 v lrck input/output 1.8 v - 3.3 v, cmos 1.8 v - 3.3 v sclk input/output 1.8 v - 3.3 v, cmos 1.8 v - 3.3 v sdout (m/s ) input/output 1.8 v - 3.3 v, cmos 1.8 v - 3.3 v sdin input - 1.8 v - 3.3 v table 1. i/o power rails
10 ds679a2 cs42l51 2. typical connection diagrams 1 f +1.8 v or +2.5 v 1 f vq dac_filt+ 0.1 f 1 f dgnd vl 0.1 f +1.8 v, +2.5 v or +3.3 v scl/cclk sda/cdin reset 2 k ? see note 1 lrck agnd ad0/cs mclk sclk 0.1 f va_hp vd * capacitors must be c0g or equivalent 1000 pf afilta afiltb micin1 ain3a microphone input 1000 pf sdin sdout cs42l51 2 k ? 1 f bias2 ain3b/micin2 ** +1.8 v or +2.5 v aoutb aouta 470 ? 470 ? c c r ext r ext see note 2 ain1a left analog input 1 1800 pf 1800 pf 100 k ? 100 ? ain1b right analog input 1 * * note 1 : resistors are required for i2c control port operation for best response to fs/2 : () 470 4 470 + = ext ext r fs r c this circuitry is intended for applications where the cs42l51 connects directly to an unbalanced output of the device. for internal routing applications please see the dac analog output characteristics section for loading limitations. note 2 : r l see note 3 note 3: the value of r l is dictated by the microphone cartridge. digital audio processor 0.1 f va headphone out left & right line level out left & right speaker driver ain2a left analog input 2 1800 pf 1800 pf ain2b bias1 right analog input 2 * * flyp flyn vss_hp gnd_hp 1 f 10 f adc_filt+ microphone bias 1 f 1 f 1 f 1 f 1 f 0.1 f 51.1 ? 0.022 f 100 k ? 100 ? 100 ? 100 ? 100 k ? 100 k ? 100 k ? 1 f ** ** * *use low esr ceramic capacitors. see note 4 note 4 : series resistance in the path of the power supplies must be avoided. any voltage drop on va_hp will directly impact the negative charge pump supply (vss_hp) and result in clipping on the audio output . 1.5 f 1.5 f see note 5 note 5 : larger capacitors, such as 1.5 f, improves the charge pump performance (and subsequent thd+n) at the full scale output power achieved with gain (g) settings greater than default. ** ** figure 1. typical connection diagram (software mode)
ds679a2 11 cs42l51 +1.8v or +2.5v 1 f vq dac_filt+ 0.1 f 1 f dgnd vl 0.1 f +1.8v, 2.5 v or +3.3v i2s/lj mclkdiv2 reset lrck agnd dem mclk sclk 0.1 f va_hp vd * capacitors must be c0g or equivalent 1000 pf afilta afiltb 1000 pf sdin sdout/ m/s cs42l51 1 f ** +1.8v or +2.5v aoutb aouta 470 ? 470 ? c c r ext r ext see note 2 ain1a left analog input 1 1800 pf 1800 pf 100 k ? 100 k ? 100 ? 100 ? ain1b right analog input 1 * * for best response to fs/2 : () 470 4 470 + = ext ext r fs r c this circuitry is intended for applications where the cs 42l51 connects directly to an unbalanced output of the device . for internal routing applications please see the dac analog output characteristics section for loading limitations . note 2 : digital audio processor 0.1 f va headphone out left & right line level out left & right speaker driver flyp flyn vss_hp gnd_hp 10 f adc_filt+ 1 f 1 f 51.1 ? 0.022 f vl 1 f see note 4 note 4 : series resistance in the path of the power supplies (typically used for added filtering) must be avoided. any voltage drop on va_hp will directly impact the negative charge pump supply (vss_hp) and result in clipping on the audio output . 1 f 1 f ** ** * *use low esr ceramic capacitors. figure 2. typical connection diagram (hardware mode)
12 ds679a2 cs42l51 3. characteristic and specification tables (all min/max characteristics and specifications are guaranteed over the specified operating conditions. typical performance characteristics and specifications are deri ved from measurements taken at nominal supply voltages and t a = 25 c.) specified operating conditions (agnd=dgnd=0 v, all volta ges with respect to ground.) absolute maximum ratings (agnd = dgnd = 0 v; all voltag es with respect to ground.) warning: operation at or beyond these limit s may result in permanent damage to the device. normal operation is not guaranteed at these extremes. notes: 1. the device will operate properly ov er the full range of the analog, hea dphone amplifier, digital core and serial/control port interface supplies. 2. any pin except supplies. transient currents of up to 100 ma on the analog input pins will not cause scr latch-up. 3. the maximum over/under voltage is limited by the input current. parameters symbol min nom max units dc power supply (note 1) analog core va 1.71 2.37 1.8 2.5 1.89 2.63 v v headphone amplifier va_hp 1.71 2.37 1.8 2.5 1.89 2.63 v v digital core vd 1.71 2.37 1.8 2.5 1.89 2.63 v v serial/control port interface vl 1.71 2.37 3.14 1.8 2.5 3.3 1.89 2.63 3.47 v v v ambient temperature commercial - cnz automotive - dnz t a -10 -40 - - +70 +85 c c parameters symbol min max units dc power supply analog digital serial/control port interface va, va_hp vd vl -0.3 -0.3 -0.3 3.0 3.0 4.0 v v v input current (note 2) i in -10ma analog input voltage (note 3) v in agnd-0.7 va+0.7 v digital input voltage (note 3) ) v ind -0.3 vl+ 0.4 v ambient operating temperature commercial - cnz (power applied) automotive - dnz t a -20 -50 +85 +95 c c storage temperature t stg -65 +150 c
ds679a2 13 cs42l51 analog input characteristics (commercial - cnz) (test conditions (unless otherwise specified): all supplies = va = 2.5 v and 1.8 v; input sine wave (relative to dig- ital full-scale): 1 khz through passive input filter; measurement bandwidth is 10 hz to 20 khz unless otherwise specified. sample frequency = 48 khz) va = 2.5v va = 1.8v parameter (note 4) min typ max min typ max unit analog in to adc (pga bypassed) dynamic range a-weighted unweighted 93 90 99 96 - - 90 87 96 93 - - db db total harmonic distortion + noise -1 dbfs -20 dbfs -60 dbfs - - - -86 -76 -36 -80 - - - - - -84 -73 -33 -78 - - db db db analog in to pga to adc dynamic range pga setting: 0 db a-weighted unweighted 92 89 98 95 - - 89 86 95 92 - - db db pga setting: +12 db a-weighted unweighted 85 82 91 88 - - 82 79 88 85 - - db db total harmonic distortion + noise pga setting: 0 db -1 dbfs -60 dbfs - - -88 -35 -82 - - - -86 -32 -80 - db db pga setting: +12 db -1 dbfs - -85 -79 - -83 -77 db analog in to mic pre-amp (+16 db) to pga to adc dynamic range pga setting: 0 db a-weighted unweighted - - 86 83 - - - - 83 80 - - db db total harmonic distortion + noise pga setting: 0 db -1 dbfs - -76 - - -74 - db analog in to mic pre-amp (+32 db) to pga to adc dynamic range pga setting: 0 db a-weighted unweighted - - 78 74 - - - - 75 71 - - db db total harmonic distortion + noise pga setting: 0 db -1 dbfs - -74 - - -71 - db other characteristics dc accuracy interchannel gain mismatch - 0.1 - - 0.1 - db gain drift - 100 - - 100 - ppm/ c input interchannel isolation - 90 - - 90 - db dac isolation (note 5) -70- -70-db full-scale input voltage (x?va) (note 7) 0.70?va 0.72?va 0.75?va 0 .70?va 0.72?va 0.75?va vpp input impedance (note 6) adc pga mic 18 40 50 - - - - - - 18 40 50 - - - - - - k ? k ? k ?
14 ds679a2 cs42l51 analog input ch aracteristics (automotive - dnz) (test conditions (unless otherwise specified): all supplies = va = 2.5 v and 1.8 v; input sine wave (relative to full- scale): 1 khz through passive input filter; measurement bandwidth is 10 hz to 20 kh z unless otherwise specified. sample frequency = 48 khz) notes: 4. referred to the typical full-scale voltage. 5. measured with dac delivering full-scale output power into 16 ? . va = 2.5v va = 1.8v parameter (note 4) min typ max min typ max unit analog in to adc dynamic range a-weighted unweighted 91 78 99 96 - - 88 85 96 93 - - db db total harmonic distortion + noise -1 db -20 db -60 db - - - -86 -76 -36 -78 - - - - - -84 -73 -33 -76 - - db db db analog in to pga to adc dynamic range pga setting: 0 db a-weighted unweighted 90 87 98 95 - - 87 84 95 92 - - db db pga setting: +12 db a-weighted unweighted 83 80 91 88 - - 80 77 88 85 - - db db total harmonic distortion + noise pga setting: 0 db -1 db -60 db - - -88 -35 -80 - - - -86 -32 -78 - db db pga setting: +12 db -1 db - -85 -77 - -83 -75 db analog in to mic pre-amp (+16 db) to pga to adc dynamic range pga setting: 0 db a-weighted unweighted - - 86 83 - - - - 83 80 - - db db total harmonic distortion + noise pga setting: 0 db -1 db - -76 - - -74 - db analog in to mic pre-amp (+32 db) to pga to adc dynamic range pga setting: 0 db a-weighted unweighted - - 78 74 - - - - 75 71 - - db db total harmonic distortion + noise pga setting: 0 db -1 db - -74 - - -71 - db other characteristics dc accuracy interchannel gain mismatch - 0.1 - - 0.1 - db gain drift - 100 - - 100 - ppm/ c input interchannel isolation - 90 - - 90 - db dac isolation (note 5) -70- -70-db full-scale input voltage (note 7) 0.70?va 0.72?va 0.75?va 0.70?va 0.72?va 0.75?va vpp input impedance (note 6) adc pga mic 18 40 50 - - - - - - 18 40 50 - - - - - - k ? k ? k ?
ds679a2 15 cs42l51 notes: 6. measured between ainxx and agnd. 7. full-scale input voltage characteristics for the pga and microphone inputs are scaled based on the gain setting for each. adc digital filter characteristics notes: 8. response is clock dependent and will scale wi th fs. note that the response plots ( figures 33 to 36 on page 78 ) have been normalized to fs and can be de-normaliz ed by multiplying the x-axis scale by fs. parameter (note 8) min typ max unit passband (frequency response) to -0.1 db corner 0 - 0.4948 fs passband ripple -0.09 - 0 db stopband 0.6677 - - fs stopband attenuation 48.4 - - db total group delay - 2.7/fs - s high-pass filter characteristics frequency response -3.0 db -0.13 db - - 3.7 24.2 - - hz hz phase deviation @ 20 hz - 10 - deg passband ripple - - 0.17 db filter settling time -10 5 /fs 0 s
16 ds679a2 cs42l51 analog output characteris tics (commercial - cnz) (test conditions (unless otherwise spec ified): input test signal is a full-scale 997 hz sine wave; measurement bandwidth is 10 hz to 20 khz; sample frequency = 48 khz; test load r l = 10 k ?, c l = 10 pf for the line output (see figure 3 ), and test load r l = 16 ?, c l = 10 pf (see figure 3 ) for the headphone output. hp_gain[2:0] = 011.) parameter (note 9) va = 2.5v min typ max va = 1.8v min typ max unit r l = 10 k ? dynamic range 18 to 24-bit a-weighted unweighted 16-bit a-weighted unweighted 92 89 - - 98 95 96 93 - - - - 89 86 - - 95 92 93 90 - - - - db db db db total harmonic distortion + noise 18 to 24-bit 0 db -20 db -60 db 16-bit 0 db -20 db -60 db - - - - - - -86 -75 -35 -86 -73 -33 -80 - - - - - - - - - - - -88 -72 -32 -88 -70 -30 -82 - - - - - db db db db db db r l = 16 ? dynamic range 18 to 24-bit a-weighted unweighted 16-bit a-weighted unweighted 92 89 - - 98 95 96 93 - - - - 89 86 - - 95 92 93 90 - - - - db db db db total harmonic distortion + noise 18 to 24-bit 0 db -20 db -60 db 16-bit 0 db -20 db -60 db - - - - - - -75 -75 -35 -75 -73 -33 -69 - - - - - - - - - - - -75 -72 -32 -75 -70 -30 -69 - - - - - db db db db db db other characteristics for r l = 16 ? or 10 k ? output parameters modulation index (mi) (note 10) analog gain multiplier (g) - 0.6787 0.6047 - - 0.6787 0.6047 - full-scale output voltage (2?g?mi?va) (note 10) refer to table ?line output voltage characteristics? on page 18 vpp full-scale output power (note 10) refer to table ?headphone output power characteristics? on page 19 interchannel isolation (1 khz) 16 ? 10 k ? - - 80 95 - - - - 80 93 - - db db interchannel gain mismatch - 0.1 0.25 - 0.1 0.25 db gain drift - 100 - - 100 - ppm/ c ac-load resistance (r l ) (note 11) 16 - - 16 - - ? load capacitance (c l ) (note 11) - - 150 - - 150 pf
ds679a2 17 cs42l51 analog output characteris tics (automotive - dnz) (test conditions (unless otherwise spec ified): input test signal is a full-scale 997 hz sine wave; measurement bandwidth is 10 hz to 20 khz; sample frequency = 48 khz and 96 khz; test load r l = 10 k ?, c l = 10 pf for the line output (see figure 3 ), and test load r l = 16 ?, c l = 10 pf (see figure 3 ) for the headphone output. hp_gain[2:0] = 011.) parameter (note 9) va = 2.5v min typ max va = 1.8v min typ max unit r l = 10 k ? dynamic range 18 to 24-bit a-weighted unweighted 16-bit a-weighted unweighted 90 87 - - 98 95 96 93 - - - - 87 84 - - 95 92 93 90 - - - - db db db db total harmonic distortion + noise 18 to 24-bit 0 db -20 db -60 db 16-bit 0 db -20 db -60 db - - - - - - -86 -75 -35 -86 -73 -33 -78 - - - - - - - - - - - -88 -72 -32 -88 -70 -30 -80 - - - - - db db db db db db r l = 16 ? dynamic range 18 to 24-bit a-weighted unweighted 16-bit a-weighted unweighted 90 87 - - 98 95 96 93 - - - - 87 84 - - 95 92 93 90 - - - - db db db db total harmonic distortion + noise 18 to 24-bit 0 db -20 db -60 db 16-bit 0 db -20 db -60 db - - - - - - -75 -75 -35 -75 -73 -33 -67 - - - - - - - - - - - -75 -72 -32 -75 -70 -30 -67 - - - - - db db db db db db other characteristics for r l = 16 ? or 10 k ? output parameters modulation index (mi) (note 10) analog gain multiplier (g) - 0.6787 0.6047 - - 0.6787 0.6047 - full-scale output voltage (2?g?mi?va) (note 10) refer to table ?line output voltage characteristics? on page 18 vpp full-scale output power (note 10) refer to table ?headphone output power characteristics? on page 19 interchannel isolation (1 khz) 16 ? 10 k ? - - 80 95 - - - - 80 93 - - db db interchannel gain mismatch - 0.1 0.25 - 0.1 0.25 db gain drift - 100 - - 100 - ppm/ c ac-load resistance (r l ) (note 11) 16 - - 16 - - ? load capacitance (c l ) (note 11) - - 150 - - 150 pf
18 ds679a2 cs42l51 line output voltage characteristics test conditions (unless otherwise specified): input test si gnal is a full-scale 997 hz sine wave; measurement band- width is 10 hz to 20 khz; sample frequency = 48 khz; test load r l = 10 k ?, c l = 10 pf (see figure 3 ). parameter va = 2.5v min typ max va = 1.8v min typ max unit aoutx voltage into r l = 10 k ? hp_gain[2:0] analog gain (g) va_hp 000 0.3959 1.8 v - 1.34 - - 0.97 - v pp 2.5 v - 1.34 - - 0.97 - v pp 001 0.4571 1.8 v - 1.55 - - 1.12 - v pp 2.5 v - 1.55 - - 1.12 - v pp 010 0.5111 1.8 v - 1.73 - - 1.25 - v pp 2.5 v - 1.73 - - 1.25 - v pp 011 (default) 0.6047 1.8 v - 2.05 - 1.41 1.48 1.55 v pp 2.5 v 1.95 2.05 2.15 - 1.48 - v pp 100 0.7099 1.8 v - 2.41 - - 1.73 - v pp 2.5 v - 2.41 - - 1.73 - v pp 101 0.8399 1.8 v - 2.85 - 2.05 v pp 2.5 v - 2.85 - - 2.05 - v pp 110 1.0000 1.8 v - 3.39 - - 2.44 - v pp 2.5 v - 3.39 - - 2.44 - v pp 111 1.1430 1.8 v (see (note 12) 2.79 v pp 2.5 v - 3.88 - - 2.79 - v pp
ds679a2 19 cs42l51 headphone output po wer characteristics test conditions (unless otherwise specified): input test signal is a full-scale 997 h z sine wave; measurement band- width is 10 hz to 20 khz; sample frequency = 48 khz; test load r l = 16 ?, c l = 10 pf (see figure 3 ). notes: 9. one-half lsb of triangular pdf dither is added to data. 10. full-scale output voltage and power is determ ined by the gain setting, g, in register ?headphone analog gain (hp_gain[2:0])? on page 54 . high gain settings at certain va and va_hp supply levels may cause clipping when the audio signal approache s full-scale, maximum power output, as shown in figures 28 - 31 on page 73 . 11. see figure 3 . r l and c l reflect the recommended minimum re sistance and maximum capacitance re- quired for the internal op-amp' s stability and signal integrity. in this circuit topology, c l will effectively move the band-limiting pole of the amp in the outpu t stage. increasing this value beyond the recom- mended 150 pf can cause the internal op-amp to become unstable. 12. va_hp settings lower than va reduces the headroom of the headphone amplifier. as a result, the dac may not achieve the full thd+n performance at full-scale output voltage and power. parameter va = 2.5v min typ max va = 1.8v min typ max unit aoutx power into r l = 16 ? hp_gain[2:0] analog gain (g) va_hp 000 0.3959 1.8 v - 14 - - 7 - mw rms 2.5 v - 14 - - 7 - mw rms 001 0.4571 1.8 v - 19 - - 10 - mw rms 2.5 v - 19 - - 10 - mw rms 010 0.5111 1.8 v - 23 - - 12 - mw rms 2.5 v - 23 - - 12 - mw rms 011 (default) 0.6047 1.8 v (note 12) -17 -mw rms 2.5 v - 32 - - 17 - mw rms 100 0.7099 1.8 v (note 12) -23 -mw rms 2.5 v - 44 - - 23 - mw rms 101 0.8399 1.8 v (note 10) ) see figure 28 on page 72 mw rms 2.5 v -32 -mw rms 110 1.0000 1.8 v (note 10 , 12 ) see figures 28 and 29 on page 72 mw rms 2.5 v mw rms 111 1.1430 1.8 v mw rms 2.5 v mw rms aoutx agnd r l c l 0.022 f 51 ? figure 3. headphone output test load
20 ds679a2 cs42l51 combined dac interp olation & on-chip ana log filter response notes: 13. response is clock dependent and will scale wi th fs. note that the response plots ( figures 35 and 36 on page 78 ) have been normalized to fs and can be de-normaliz ed by multiplying the x-axis scale by fs. 14. measurement bandwidth is from stopband to 3 fs. switching specificat ions - serial port (inputs: logic 0 = dgnd, logic 1 = vl, sdout c load = 15 pf.) parameter (note 13) )mintypmaxunit frequency response 10 hz to 20 khz -0.01 - +0.08 db passband to -0.05 db corner to -3 db corner 0 0 - - 0.4780 0.4996 fs fs stopband 0.5465 - - fs stopband attenuation (note 14) 50 - - db group delay - 9/fs - s de-emphasis error fs = 32 khz fs = 44.1 khz fs = 48 khz - - - - - - +1.5/+0 +0.05/-0.25 -0.2/-0.4 db db db parameters symbol min max units reset pin low pulse width (note 15) 1-ms mclk frequency 1.024 38.4 mhz mclk duty cycle (note 16) 45 55 % slave mode input sample rate (lrck) quarter-speed mode half-speed mode single-speed mode double-speed mode f s f s f s f s 4 8 4 50 12.5 25 50 100 khz khz khz khz lrck duty cycle 45 55 % sclk frequency 1/t p -64?f s hz sclk duty cycle 45 55 % lrck setup time before sclk rising edge t s(lk-sk) 40 - ns lrck edge to sdout msb output delay t d(msb) -40ns sdout setup time before sclk rising edge t s(sdo-sk) 30 - ns sdout hold time after sclk rising edge t h(sk-sdo) 30 - ns sdin setup time before sclk rising edge t s(sd-sk) 20 - ns sdin hold time after sclk rising edge t h 20 - ns
ds679a2 21 cs42l51 notes: 15. after powering up the cs42l51 , reset should be held low after the power supplies and clocks are set- tled. 16. see ?example system clock frequencies? on page 75 for typical mclk frequencies. 17. see ?master? on page 38 . master mode (note 17) output sample rate (lrck) all speed modes f s -hz lrck duty cycle 45 55 % sclk frequency 1/t p - 64?f s hz sclk duty cycle 45 55 % sclk rising edge to sdout output delay t d -s lrck edge to sdout msb output delay t d(msb) -40ns sdout setup time before sclk rising edge t s(sdo-sk) 30 - ns sdout hold time afte r sclk rising edge t h(sk-sdo) 30 - ns sdin setup time before sclk rising edge t s(sd-sk) 20 - ns sdin hold time after sclk rising edge t h 20 - ns parameters symbol min max units t h(sk-sdo) // // // // // // // // t s(sd-sk) msb msb msb-1 msb-1 lrck sclk sdout sdin t d(msb) t s(lk-sk) t p t h t s(sdo-sk) figure 4. serial audio interface slave mode timing mclk 128 ----------------- 1 mclk ----------------- t h(sk-sdo) // // // // // // // // t s(sd-sk) msb msb msb-1 msb-1 lrck sclk sdout sdin t d(msb) t p t h t s(sdo-sk) figure 6. serial audio in terface master mode timing
22 ds679a2 cs42l51 switching specifications - i2c control port (inputs: logic 0 = dgnd, logic 1 = vl, sda c l =30pf) notes: 18. data must be held for sufficient ti me to bridge the transition time, t fc , of scl. parameter symbol min max unit scl clock frequency f scl - 100 khz reset rising edge to start t irs 500 - ns bus free time between transmissions t buf 4.7 - s start condition hold time (prior to first clock pulse) t hdst 4.0 - s clock low time t low 4.7 - s clock high time t high 4.0 - s setup time for repeated start condition t sust 4.7 - s sda hold time from scl falling (note 18) t hdd 0-s sda setup time to scl rising t sud 250 - ns rise time of scl and sda t rc -1s fall time scl and sda t fc - 300 ns setup time for stop condition t susp 4.7 - s acknowledge delay from scl falling t ack 300 1000 ns t buf t hdst t hdst t low t r t f t hdd t high t sud t sust t susp stop start start stop repeated sda scl t irs rst figure 7. control port timing - i2c
ds679a2 23 cs42l51 switching characteristics - spi control port (inputs: logic 0 = dgnd, logic 1 = vl) notes: 19. data must be held for sufficient time to bridge the transition time of cclk. 20. for f sck <1 mhz. parameter symbol min max units cclk clock frequency f sck 06.0mhz reset rising edge to cs falling t srs 20 - ns cs falling to cclk edge t css 20 - ns cs high time between transmissions t csh 1.0 - s cclk low time t scl 66 - ns cclk high time t sch 66 - ns cdin to cclk rising setup time t dsu 40 - ns cclk rising to data hold time (note 19) t dh 15 - ns rise time of cclk and cdin (note 20) t r2 -100ns fall time of cclk and cdin (note 20) t f2 -100ns cs cclk cdin rst t srs t scl t sch t css t r2 t f2 t csh t dsu t dh figure 8. control po rt timing - spi format
24 ds679a2 cs42l51 dc electrical characteristics (agnd = 0 v; all voltages with respect to ground.) notes: 21. the dc current draw represents the allowed current draw from the vq pin due to typical leakage through electrolytic de-coupling capacitors. 22. valid with the recommended capacitor values on dac_filt+, adc_filt+ and vq. increasing the ca- pacitance will also increase the psrr. digital interface specific ations & characteristics 23. see ?digital i/o pin characteristics? on page 9 for serial and control port power rails. parameters min typ max units vq characteristics nominal voltage output impedance dc current source/sink (note 21) - - - 0.5?va 23 - - - 10 v k ? a dac_filt+ nominal voltage adc_filt+ nominal voltage - - va va - - v v vss_hp characteristics nominal voltage dc current source - - -0.8?(va_hp) - 10 v a mic bias characteristics nominal voltage mic bias_lvl[1:0] = 00 micbias_lvl[1:0] = 01 micbias_lvl[1:0] = 10 micbias_lvl[1:0] = 11 dc current source power supply rejection ratio (psrr) 1 khz - - - - - - 0.8?va 0.7?va 0.6?va 0.5?va - 50 - - - - 1 - v v v v ma db power supply rejection ratio (psrr) (note 22) 1 khz - 60 - db parameters (note 23) symbol min max units input leakage current i in -10 a input capacitance -10pf 1.8 v - 3.3 v logic high-level output voltage (i oh = -100 a) v oh vl - 0.2 - v low-level output voltage (i ol = 100 a) v ol -0.2v high-level input voltage v ih 0.65?vl - v low-level input voltage v il - 0.35?vl v
ds679a2 25 cs42l51 power consumption see (note 24) . notes: 24. unless otherwise noted, test conditions are as follows: all zeros input, sl ave mode, sample rate = 48 khz; no load. digital (vd) and logic (vl) supply current will vary depending on speed m ode and mas- ter/slave operation. 25. reset pin 25 held lo, all clocks and data lines are held lo. 26. reset pin 25 held hi, all clocks and data lines are held hi. 27. vl current will slightly in crease in master mode. power ctl. registers typical current (ma) operation 02h 03h pdn_dacb pdn_daca pdn_pgab pdn_pgaa pdn_adcb pdn_adca pdn pdn_micb pdn_mica pdn_micbias v va_hp va vd vl (note 27) total power (mw rms ) 1 off (note 25) xxxxxxxxxx 1.8 0 0 0 0 0 2.5 0 0 0 0 0 2 standby (note 26) xxxxxx1xxx 1.8 0 0.01 0.02 0 0.05 2.5 0 0.01 0.03 0 0.10 3 mono record adc1111100111 1.8 0 1.85 2.03 0.03 7.05 2.5 0 2.07 3.05 0.05 12.94 pga to adc1110100111 1.8 0 2.35 2.03 0.03 7.95 2.5 0 2.58 3.08 0.05 14.29 mic to pga to adc (with bias) 1110100100 1.8 0 3.67 2.05 0.03 10.36 2.5 0 3.95 3.09 0.05 17.71 mic to pga to adc (no bias) 1110100101 1.8 0 3.27 2.03 0.03 9.61 2.5 0 3.52 3.08 0.05 16.62 4 stereo record adc1111000111 1.8 0 2.69 2.12 0.03 8.72 2.5 0 2.93 3.18 0.04 15.40 pga to adc1100000111 1.8 0 3.65 2.12 0.03 10.45 2.5 0 3.91 3.17 0.04 17.84 mic to pga to adc (no bias) 1100000001 1.8 0 5.48 2.11 0.03 13.73 2.5 0 5.76 3.17 0.04 22.45 5 mono playback 1011110111 1.8 1.66 1.40 2.35 0.01 9.74 2.5 2.03 1.71 3.48 0.02 18.08 6 stereo playback 0011110111 1.8 2.77 2.05 2.35 0.01 12.93 2.5 3.21 2.50 3.49 0.02 23.02 7 mono record & playback pga in (no mic) to mono out 1010100111 1.8 1.66 3.63 2.73 0.03 14.49 2.5 2.03 4.16 4.08 0.05 25.79 8 phone monitor mic (w/bias) in to mono out 1010100100 1.8 1.66 4.95 2.75 0.03 16.90 2.5 2.03 5.52 4.08 0.05 29.20 9 stereo record & playback pga in (no mic) to stereo out 0000000111 1.8 2.77 5.59 2.82 0.03 20.18 2.5 3.21 6.28 4.19 0.04 34.30
26 ds679a2 cs42l51 4. applications 4.1 overview 4.1.1 architecture the cs42l51 is a highly integrated, low power, 24-bit au dio codec comprised of stereo analog-to-digital converters (adc), and stereo digital-to-analog conv erters (dac) designed using multi-bit delta-sigma techniques. the dac operates at an oversampling ratio of 128fs and the adc operates at 64fs, where fs is equal to the system sample rate. the differen t clock rates maximize power savings while maintaining high performance. the codec operates in one of four sample rate speed modes: quarter, half, single and double. it accepts and is capable of generating seri al port clocks (sclk, lrck) derived from an input master clock (mclk). 4.1.2 line & mic inputs the analog input portion of the codec allows select ion from and configuration of multiple combinations of stereo and microphone (mic) sources. six line inputs with configuration for tw o mic inputs (or one mic input with common mode rejection), two mic bias out puts and independent channel control (including a high-pass filter disable function) are available. a pr ogrammable gain amplifier (pga), mic boost, and au- tomatic level control (alc), with no ise gate settings, provide analog gain and adjustment. digital volume controls, including gain, boost, attenuation and inversion are also available. 4.1.3 line & headphone outputs the analog output portion of the codec includes a headphone amplifier capable of driving headphone and line-level loads. an on-chip charge pump creates a negative headphone supply allowing a full-scale output swing centered around ground. this eliminat es the need for large dc-blocking capacitors and al- lows the amplifier to deliver more power to headphone loads at lower supply voltages. eight gain settings for the headphone amplifier are available. 4.1.4 signal processing engine a signal processing engine is available to process seri al input data (pcm) and adc data before output to the dac. the adc and pcm data have independent volu me controls and mixing functions such as mono mixes and left/right channel swaps. a tone control provides bass an d treble at four selectable corner fre- quencies. an automatic le vel control provides limiting capabilitie s at programmable at tack and release rates, maximum thresholds and soft ramping. a 15/50 s de-emphasis filter is also available at a 44.1 khz sample rate. 4.1.5 beep generator a beep may be generated internally at select freq uencies across approximately two octave major scales and configured to occur continuously, periodically or at single time intervals controlled by the user. volume may be controlled independently. 4.1.6 device control (hardw are or software mode) in software mode, all functions and features may be controlled via a two-wire i2c or three-wire spi control port interface. in hardware mode, a limited featur e set may be controlled via stand-alone control pins. 4.1.7 power management two software mode control registers provide indepen dent power down control of the adc, dac, pga, mic pre-amp and mic bias, allowing operation in se lect applications with minimal power consumption.
ds679a2 27 cs42l51 4.2 hardware mode a limited feature-set is available when the codec powers up in hardware mode (see ?recommended power-up sequence? on page 40 ) and may be controlled via stand-alone control pins. table 2 shows a list of functions/fea- tures, the default configuration and the a ssociated stand-alone control available. hardware mode feature/function summary feature/function default configuration stand-alone control note power control codec pgax adcx dacx mic bias micx pre-amplifier powered up powered up powered up powered up powered down powered down - - auto detect enabled - - speed mode serial port slave serial port master auto-detect speed mode single-speed mode - - mclk divide (selectable) ?mclkdiv2? pin 2 see section 4.5 on page 37 serial port master / slave selection (selectable) ?m/s ? pin 29 see section 4.5 on page 37 interface control adc dac (selectable) ?i2s/lj ? pin 3 see section 4.6 on page 39 adc volume & gain digital boost soft ramp zero cross invert pgax attenuator alc noise gate disabled disabled disabled disabled 0 db 0 db disabled disabled - - adcx high-pass filter adcx high-pass filter freeze enabled continuous dc subtraction - - line/mic input select ain1a to pgaa ain1b to pgab - - dac volume & gain hp gain aoutx volume invert soft ramp zero cross ramp g = 0.6047 0 db disabled enabled disabled disabled - - dac de-emphasis (selectable) ?dem? pin 4 see section 4.4.1 on page 33 signal processing engine (spe) mix beep tone control peak detect & limiter disabled disabled disabled disabled - - data selection data input (pcm) to dac - - channel mix adc dac adca = l; adcb = r pcma = l; pcmb = r - - charge pump frequency (64xfs)/7 - - table 2. hardware mode feature summary
28 ds679a2 cs42l51 4.3 analog inputs ainxa and ainxb are the analog inputs, internally bias ed to vq, that accepts line-level and mic-level sig- nals, allowing various gain and signal adjustments for each channel. 4.3.1 digital code, offset & dc measurement the adc output data is in two?s complement binary format. for inputs above positive full-scale or below negative full-scale, the adc will out put 7fffffh or 800000h, respecti vely and cause the adc overflow bit to be set to a ?1?. given the two?s complement format, low-level signals may cause the msb of the serial data to periodically toggle between ?1? and ?0?, possibly introducing noise into the system as the bit switches back and forth. to prevent this phenomena, a constant dc offset is added to the serial data bringing the low-level signal just above the point at which the msb would norm ally toggle, thus reducing the noise introduced. the codec may be used to measure dc voltages by disabling the high-pass filter for the designated channel. dc levels are measured re lative to vq and will be decoded as positive two?s complement binary numbers above vq and negative two?s co mplement binary numbers below vq. software controls: ?status (address 20h) (read only)? on page 71 , ?adc control (address 06h)? on page 52 . multibit oversampling adc ain3a/ micin1 mica_boost attenuator alc pgaa_vol[5:0] adc_sngvol 0/-96db 1db steps adca_att[7:0] adca_hpf enable adca_hpf freeze pdn_adca adca_mute softa alc_ena alcb_srdis alcb_zcdis pdn_mica micbias pdn_micbias micbias_lvl[1:0] pcm serial interface micbias_sel to signal processing engine (spe) inv_adca alc_arate[5:0] alc_rrate[5:0] max[2:0] min[2:0] alc_enb alca_srdis alca_zcdis mux ain1a ain2a pga +16/ 32 db aina_mux[1:0] pdn_pgaa +12/-3db 0.5db steps softa zcrossa multibit oversampling adc ain3b/ micin2/ micbias micb_boost pgab_vol[5:0] adc_sngvol 0/-96db 1db steps adcb_att[7:0] adcb_hpf enable adcb_hpf freeze pdn_adcb adcb_mute softb pdn_micb inv_adcb mux ain1b ain2b/micbias pga +16/ 32 db ainb_mux[1:0] pdn_pgab +12/-3db 0.5db steps softb zcrossb noise gate ng_all ng_en thresh[3:0] ngdelay[1:0] attenuator +20db digital boost adca_dboost +20db digital boost adcb_dboost mux mux micmix mux mux from signal processing engine (spe) digmix figure 9. analog input architecture
ds679a2 29 cs42l51 4.3.2 high-pass filter and dc offset calibration the high-pass filter continuously su btracts a measure of the dc offset from the output of the decimation filter. if the high-pass filter is ?frozen? during normal operation, the current value of the dc offset for the corresponding channel is held . it is this dc offset that will contin ue to be subtracted from the conversion result. this feature makes it possible to pe rform a system dc offset calibration by: 1. 1) running the codec with the high-pass filter enabl ed and the dc offset not ?frozen? until the filter settles. see the digital f ilter characteristics fo r filter settling time. 2. freezing the dc offset. the high-pass filters are controlled usin g the adcx_hpfrz and adcx_hpfen bits. if a particular adc channel is used to measure dc voltages, the high-pass filter may be disabled using the adcx_hpfen bit. 4.3.3 digital routing the digital output of the adc may be internally routed to the signal processing engine for playback of an- alog input signals. volume to the dac may be contro lled using the adcmix[6:0] bits. the serial input data may also be routed to the adc serial interface using th e digmix bit. this is useful for recording a digital mix along with the analog input. 4.3.4 differential inputs the stereo pair inputs act as a single differential i nput when the micmix bit is enabled. this provides com- mon mode rejection of noise in digitally intense pcb?s where the microphone signal traverses long traces, or across long microphone cables as illustrated in figure 10 . since the mixer provides a differential combination of the two signals, the potential input mix may exceed the maximum full-scale input and result in clipping. the level out of the mixer, therefore, is automatically attenuated 6 db. gain may be applied using either the analog pga or mic pre-amp or the digital adcmix volume control to re-adjust a small signal to desired levels. the analog inputs may also be used as a differential input pair as illustrated in figure 11 . the two chan- nels are differentially combined when the micmix bit is enabled. 4.3.4.1 external passive components the microphone input is internally biased to vq. inpu t signals must be ac coupled using external capaci- tors with values consistent with the desired high-pass filter design. the micinx input resistance of 50 k ? may be combined with an external capacitor of 1 f to achieve the cutoff fr equency defined by the equa- tion, an electrolytic capacitor must be pl aced such that the positive terminal is positioned relative to the side with the greater bias voltage. the mi cbias voltage level is controlled by the micbias_lvl[1:0] bits. software controls: ?adc control (address 06h)? on page 52 . software controls: ?adcx mixer volume control: adca (address 0eh) & adcb (address 0fh)? on page 58 , ?inter- face control (address 04h)? on page 49 . f c 1 2 50 k ? () 1 f () ------------------------------------------- 3 . 1 8 hz ==
30 ds679a2 cs42l51 the micbias series resistor must be selected based on the requirements of the particular microphone used. the micbias output pin is se lected using the micbias_sel bit. 4.3.5 analog input multiplexer a stereo 4-to-1 analog input multiple xer selects between a line-level input source, or a mic-level input source, depending on the pdn_pgax and ainx_mux[1:0 ] bit settings. signals may be routed to or by- passed around the pga. to conserve power, the pga?s may be powered down allowing the user to select from multiple line-level sources and route the stereo signal directly to the adc. when using the mic pre- amp, however, the pga must be powered up. analog input channel b may also be used as an output for the mic bias voltage. the micbias_sel bit routes the bias voltage to either of two pins. the mu ltiplexer must then select from the remainder of the two input channels. the adc, pga and mic pre-amplifier each has an asso ciated input resistance. when selecting between these paths, the input resistance to the codec will ch ange accordingly. refer to the input resistance characteristics in the characteristic and specification tables for the input resistance of each path. software controls: ?interface control (address 04h)? on page 49 , ?mic control (address 05h)? on page 51 . software controls: ?power control 1 (address 02h)? on page 47 , ?mic control (address 05h)? on page 51 , ?adcx input select, invert & mu te (address 07h)? on page 53 . micin1 micin2 + + micbias 18 17 20 // // figure 10. mic input mix w/common mode rejection full-scale differential input level (micmix=1) = (ainxa - ainxb) = 3.6 v pp = 1.27 v rms ainxa ainxb 2.15 v 1.25 v 0.35 v 2.5 v 2.15 v 1.25 v 0.35 v va figure 11. differential input
ds679a2 31 cs42l51 4.3.6 mic & pga gain the mic-level input passes through a +16 db or +32 db analog gain stage prior to the input multiplexer, allowing it to be used for microphone level signals without the need for any external gain. the pga must be powered up when using the mic pre-amp. the pga stage provides an additional +12 db to -3 db of analog gain in 0.5 db steps. 4.3.7 automatic level control (alc) when enabled, the alc monitors the analog input signal after the digital attenuator, detects when peak levels exceed the maximum threshold settings and lowe rs, first, the pga gain settings and then increases the digital attenuation levels at a programmable attack rate and maintains the resulting level below the maximum threshold. when input signal levels fall below the minimum threshold, digital atte nuation levels are decreased first and the pga gain is then increased at a programmable release rate and maintains the resulting level be- low the minimum threshold. attack and release rates are affected by the adc soft ramp/zero cross settings and sample rate, fs. alc soft ramp and zero cross dependency may be independently enabled/disabled. recommended settings : best level control may be realized with the fastest attack and slowest release setting with soft ramp enabled in the control registers. note: when the alc is enabled the pga and at- tenuator is automatically controlled an d should not be adjusted manually. software controls: ?power control 1 (address 02h)? on page 47 , ?adcx input select, invert & mute (address 07h)? on page 53 , ?alcx & pgax control: alca , pgaa (address 0ah) & alcb, pgab (address 0bh)? on page 56 , ?mic control (address 05h)? on page 51 . software controls: ?alc enable & attack rate (address 1ch)? on page 67 , ?alc release rate (address 1dh)? on page 68 , ?alc threshold (address 1eh)? on page 69 , ?alcx & pgax control: alca, pgaa (address 0ah) & alcb, pgab (address 0bh)? on page 56 . output (after alc) input rrate[5:0] pga gain and/or attenuator alc max[2:0] arate[5:0] below full scale min[2:0] below full scale min[2:0] below full scale max[2:0] below full scale adcx_att[7:0] and pgax_vol[4:0] volume controls should not be adjusted manually when alcx is enabled. figure 12. alc
32 ds679a2 cs42l51 4.3.8 noise gate the noise gate may be used to mute signal levels th at fall below a programmable threshold. this prevents the alc from applying gain to noise. a programmable delay may be used to set the minimum time before the noise gate attacks the signal. *maximum noise gate attenu ation levels will depend on the gain a pplied in either the pga or mic pre- amplifier. for example: if both +32 db pre-amplific ation and +12 db programmable gain is applied, the maximum attenuation that the noise gate achieves will be 52 db (-96 + 32 + 12) below full-scale. ramp down time to the maximum setting is affected by the softx bit. recommended settings : for best results, enable soft ramp for the digital attenuator. when the analog in- puts are configured for differential signals (see ?differential inputs? on page 29 ), enable the ng_all bit to trigger the noise gate only when both inputs fall below the threshold. software controls: ?noise gate configuration & misc. (address 1fh)? on page 70 , ?adc control (address 06h)? on page 52 . -96 -40 thresh[2:0] maximum attenuation* -52 db output (db) input (db) n g e n = 1 n g e n = 0 -80 db -64 db figure 13. noise gate attenuation
ds679a2 33 cs42l51 4.4 analog outputs aouta and aoutb are the ground-centered line or hea dphone outputs. various signal processing options are available, including digital mixes with the adc sign al and an internal beep generator. the desired path to the dac must be selected using the data_sel[1:0] bits. 4.4.1 de-emphasis filter the codec includes on-chip digital de-emphasis optimi zed for a sample rate of 44.1 khz. the filter re- sponse is shown in figure 15 . the de-emphasis feature is incl uded to accommodate audio recordings that utilize 50/15 s pre-emphasis equalization as a means of noi se reduction. de-emphasis is only avail- able in single speed mode. software controls: ?dac control (address 09h)? on page 55 . software controls: ?dac control (address 09h)? on page 55 . hardware control: pin setting selection ?dem? pin 4. lo no de-emphasis hi de-emphasis applied charge pump left/right hp out switched capacitor dac and filter headphone amp - gnd centered pdn_daca pdn_dacb data_sel[1:0] 00 chrg_freq[3:0] 01 10 hp_gain[2:0] beep generator vol bass/ treble/ control vol peak detect limiter chnl vol. settings channel swap demph vol vol +12db/-102db 0.5db steps outa_vol[7:0] outb_vol[7:0] +12db/-51.5db 0.5db steps adcmixa_vol[6:0] adcmixb_vol[6:0] +12db/-51.5db 0.5db steps pcmmixa_vol[6:0] pcmmixb_vol[6:0] 0db/-50db 2.0db steps bpvol[4:0] mute_pcmmixa mute_pcmmixb mute_adcmixa mute_adcmixb deemph bass[3:0] treb[3:0] +12.0db/-10.5db 1.5db steps bass_cf[1:0] treb_cf[1:0] tc_en signal processing engine (spe) dac_szc[1:0] daca_mute dacb_mute inv_daca inv_dacb dac_sngvol amute arate[7:0] rrate[7:0] max[2:0] min[2:0] lim_srdis lim_zcdis limit_en pcma[1:0] pcmb[1:0] adca[1:0] adcb[1:0] pcm serial interface inputs from adca and adcb offtime[2:0] ontime[3:0] freq[3:0] repeat beep digital mix to adc serial interface channel swap figure 14. output architecture gain db -10db 0db frequency t2 = 15 s t1=50 s f1 f2 3.183 khz 10.61 khz figure 15. de-emphasis curve
34 ds679a2 cs42l51 4.4.2 volume controls three digital volume control functions are implement ed, offering independent control over the adc and pcm signal paths into the mixer as well as a combined control over the mixed signals. all volume controls are programmable to ramp in increments of 0.125 db at a rate controlled by the dac soft ramp/zero cross settings. all signal paths may also be independently muted via mute control bits. when enabled, each bit attenu- ates the signal to its maximum value. when the mute bit is disabled, the signal returns to the attenuation level set in the respective volume control register. the attenuation is ramped up and down at the rate specified by the dac_szc[1:0] bits. 4.4.3 mono channel mixer a channel mixer may be used to create a mix of the left and right channels for either the pcm or adc signals. this mix allows the user to produce a mono signal from a stereo source. the mixer may also be used to implement a le ft/right channel swap. 4.4.4 beep generator the beep generator generates audio frequencies acro ss approximately two octave major scales. it offers three modes of operation: continuous, multiple and si ngle (one-shot) beeps. sixteen on and eight off times are available. note : the beep is generated before the limiter and may affect desired limiting performance. if the limiter function is used, it may be required to set the beep volume sufficiently below t he threshold to prevent the peak detect from triggering. sinc e the master volume control, aout x_vol[7:0], will af fect the beep vol- ume, dac volume may alternatively be c ontrolled using the pc mmixx_vol[6:0] bits. software controls: ?adcx mixer volume control: adca (addre ss 0eh) & adcb (address 0fh)? on page 58 , ?pcmx mixer volume control: pcma (address 10h) & pcmb (address 11h)? on page 59 , ?aoutx vol- ume control: aouta (address 16h) & aoutb (address 17h)? on page 64 , ?dac output control (address 08h)? on page 54 . software controls: ?adc & pcm channel mixer (address 18h)? on page 64 . software controls: ?beep frequency & timing configuration (address 12h)? on page 60 , ?beep off time & volume (address 13h)? on page 61 , ?beep configuration & tone configuration (address 14h)? on page 62 freq[3:0] ... bpvol[4:0] ontime[3:0] offtime[2:0] repeat = '0' beep = '1' repeat = '1' beep = '0' repeat = '1' beep = '1' single-beep : beep turns on at a configurable frequency (freq) and volume (bpvol) for the duration of ontime. beep must be cleared and set for additional beeps. multi-beep : beep turns on at a configurable frequency (freq) and volume (bpvol) for the duration of ontime and turns off for the duration of offtime. on and off cycles are repeated until repeat is cleared. continuous beep : beep turns on at a configurable frequency (freq) and volume (bpvol) and remains on until repeat is cleared. figure 16. beep configuration options
ds679a2 35 cs42l51 4.4.5 tone control shelving filters are used to implement bass and trebl e (boost and cut) with four selectable corner frequen- cies. boosting will affect peak detect and limiting when levels exceed the ma ximum threshold settings. 4.4.6 limiter when enabled, the limiter monitors the digital input si gnal before the dac modulator, detects when levels exceed the maximum threshold settings and lowers t he aout volume at a programmable attack rate be- low the maximum threshold. when the input signal level falls below the maxi mum threshold, the aout volume returns to its original level set in the volume control register at a programmable release rate. at- tack and release rates are affected by the dac soft ramp/zero cross settings and sample rate, fs. limiter soft ramp and zero cross dependency may be independently enabled/disabled. recommended settings : best limiting performance may be realiz ed with the fastest attack and slowest release setting with soft ramp enabled in the control re gisters. the ?cushion? bits allow the user to set a threshold slightly below the maximum threshold for hyst eresis control - this cushions the sound as the lim- iter attacks and releases. note: when the limiter is enabled the aout volume is automatically con- trolled and should not be adjusted manually. alte rnative volume control may be realized using the pcmmixx_vol[6:0] bits. software controls: ?tone control (address 15h)? on page 63 . software controls: ?limiter release rate register (address 1ah)? on page 66 , ?limiter attack rate register (address 1bh)? on page 67 , ?dac control (address 09h)? on page 55 max[2:0] output (after limiter) input rrate[5:0] arate[5:0] volume limiter cush[2:0] attack/release sound cushion max[2:0] aoutx_vol[7:0] volume control should not be adjusted manually when limiter is enabled. figure 17. peak detect & limiter
36 ds679a2 cs42l51 4.4.7 line-level outputs and filtering the codec contains on-chip buffer amplifiers capab le of producing line level single-ended outputs on aouta and aoutb. these amplifiers are ground cent ered and do not have any dc offset. a load stabi- lizer circuit, shown in the ?typical connection diagram (software mode)? on page 10 and the ?typical connection diagram (hardware mode)? on page 11 , is required on the analog outputs. this allows the dac amplifiers to drive line or headphone outputs. also shown in the typical connecti on diagrams is the recommended passiv e output filter to support high- er impedances such as those found on the inputs to operational amplifiers. ?rext?, shown in the typical connection diagrams, is the input impedance of the receiving device. the invert and digital gain controls may be used to provide phase and/or amplitude compensation for an external filter. the delta-sigma conversion proces s produces high frequency noise beyond the audio passband, most of which is removed by the on-chip analog filters. the remaining out-of-band noise can be attenuated using an off-chip low pass filter. 4.4.8 on-chip charge pump an on-chip charge pump derives a negative supply vo ltage from the va_hp supply. this provides dual rail supplies allowing a full-scale output swing centered around ground and eliminates the need for large, dc-blocking capacitors. added benefits include grea ter pop suppression and improved low frequency (bass) response. note: series resistance in the path of the power supplies must be avoided. any voltage drop on the va_hp supply will directly impact the derived negative volt age on the charge pump supply, vss_hp, and may result in clipping. the flyn and flyp pins connect to internal switches that charges and discharges the external capacitor attached, at a default switching frequency. this freq uency may be adjusted in the control port registers. increasing the charge-pumpi ng capacitor will slightly decease the pumping freque ncy. the capacitor con- nected to vss_hp acts as a charge reservoir for the n egative supply as well as a filter for the ripple in- duced by the charge pump. increasing this capacitor will decrea se the ripple on vss_hp. refer to the typical connection diagrams in figure 1 on page 10 or figure 2 on page 11 for the recommended capacitor values for the charge pump circuitry. software controls: ?dac output control (address 08h)? on page 54 , ?aoutx volume control: aouta (address 16h) & aoutb (address 17h)? on page 64 . software controls: ?charge pump frequency (address 21h)? on page 71 .
ds679a2 37 cs42l51 4.5 serial port clocking the codec serial audio interface port operates either as a slave or master. it accepts externally generated clocks in slave mode and will generate synchronous clo cks derived from an input master clock (mclk) in master mode. the frequency of the mclk must be an integer multip le of, and synchronous with, the system sample rate, fs. the lrck frequency is equal to fs, the frequency at which audio samples for each channel are clocked into or out of the device. the speed and mclkdiv2 software control bits or the sdout/(m/s ) and mclkdiv2 stand-alone control pins, configure the device to gener ate the proper clocks in master mode and rece ive the proper clocks in slave mode. the value on the sdout pin is latched imme diately after powering up in hardware mode. 4.5.1 slave lrck and sclk are inputs in slave mode. the spee d of the codec is automatically determined based on the input mclk/lrck ratio when the auto-detect fu nction is enabled. certain input clock ratios will then require an internal divide-by-two of mclk* us ing either the mclkdiv2 bit or the mclkdiv2 stand- alone control pin. additional clock ratios are allowed when the auto-det ect function is disabled; but the appropriate speed mode must be selected us ing the speed[1:0] bits. software control: ?mic power control & speed control (address 03h)? on page 48 , ?dac control (address 09h)? on page 55 . hardware control: pin setting selection ?sdout, m/s ? pin 29 47 k ? pull-down slave 47 k ? pull-up master ?mclkdiv2? pin 2 lo no divide hi mclk is divided by 2 prior to all internal circuitry. auto-detect qsm hsm ssm dsm disabled (software mode only) 512, 768, 1024, 1536, 2048, 3072 256, 384, 512, 768, 1024, 1536 128, 192, 256, 384, 512, 768 128, 192, 256, 384 enabled 1024, 1536, 2048*, 3072* 512, 768, 1024*, 1536* 256, 384, 512*, 768* 128, 192, 256*, 384* *mclkdiv2 must be enabled. table 3. mclk/lrck ratios
38 ds679a2 cs42l51 4.5.2 master lrck and sclk are internally derived from the inter nal mclk (after the divide, if mclkdiv2 is enabled). in hardware mode the codec operates in single-spe ed only. in software mode the codec operates in either quarter-, half-, single- or double-speed depending on the setting of the speed[1:0] bits. 4.5.3 high-impedance digital output the serial port may be placed on a clock/data bus th at allows multiple master s, without the need for ex- ternal buffers. the 3st_sp bit places the internal bu ffers for the serial port signals in a high-impedance state, allowing another device to transmi t clocks or data without bus contention. 256 128 512 lrck output (equal to fs) single speed quarter speed half speed 01 10 11 sclk output 2 1 0 1 mclk mclkdiv2 128 00 4 2 8 single speed quarter speed half speed 01 10 11 2 00 double speed double speed speed[1:0] figure 18. master mode timing cs42l51 transmitting device #1 transmitting device #2 receiving device 3st_sp sdout sclk/lrck figure 19. tri-state serial port
ds679a2 39 cs42l51 4.5.4 quarter- and half-speed mode quarter-speed mode (qsm) and half-speed mode (hs m) allow lower sample ra tes while maintaining a relatively flat noise floor in the typical audio band of 20 hz - 20 khz. single-speed mode (ssm) will allow lower frequency sample rates; howe ver, the dac's noise floor, that normally rises out- of-band, will scale with the lower sample rate and begin to rise within the audio band. qsm and hsm corrects for most of this scaling, effectively increasing the dynamic rang e of the codec at lower sa mple rates, relative to ssm. 4.6 digital interface formats the serial port operates in standard i2s, left-justifi ed or right-justified(dac only) digital interface formats with varying bit depths from 16 to 24. data is clocked out of the adc or into the dac on the rising edge of sclk. figures 20 - 22 illustrate the general structur e of each format. refer to ?switching specifications - se- rial port? on page 20 for exact timing relationsh ip between clocks and data. software control: ?interface control (address 04h)? on page 49 . hardware control: pin setting selection ?i2s/lj ? pin 3 lo left-justified interface hi i2s interface lrck sclk msb lsb msb lsb aouta / ainxa left channel right channel sdout sdin aoutb / ainxb msb figure 20. i2s format lrck sclk msb lsb msb lsb left channel right channel sdout sdin msb aouta / ainxa aoutb / ainxb figure 21. left-justified format lrck sclk msb lsb msb lsb left channel right channel sdin aouta aoutb figure 22. right-justi fied format (dac only)
40 ds679a2 cs42l51 4.7 initialization the initialization and po wer-down sequence flow chart is shown in figure 23 on page 41 . the codec en- ters a power-down state upon initial power-up. the inter polation & decimation filt ers, delta-sigma modula- tors and control port registers are reset. the inte rnal voltage reference, multi-bit dac and adc and switched-capacitor low-pass filters are powered down. the device will remain in the po wer-down state until the reset pin is brought high. the control port is ac- cessible once reset is high and the desired register settings can be loaded per the interface descriptions in ?software mode? on page 42 . if a valid write sequence to the contro l port is not made within approximately 10 ms, the codec will enter hardware mode. once mclk is valid, the quiescent voltage, vq, and the internal voltage references, dac_filt+ and adc_filt+, will begin powering up to normal operation. th e charge pump slowly powers up and charges the capacitors. power is then applied to the headphone amp lifiers and switched-capacitor filters, and the an- alog/digital outputs enter a muted state. once lrck is valid, mclk occurrences are counted over one lrck period to determine the mclk/lrck frequency ratio and normal operation begins. 4.8 recommended power-up sequence 1. hold reset low until the power supplies are stable. 2. bring reset high. after approximately 10 ms, the device will enter hardware mode. 3. for software mode operation, set th e pdn bit to ?1?b in under 10 ms. this will place the device in ?stand- by?. 4. load the desired register settings wh ile keeping the pdn bit set to ?1?b. 5. start mclk to the appropriate frequency, as discussed in section 4.5 . 6. set the pdn bit to ?0?b. 7. apply lrck, sclk and sdin for normal operation to begin. 8. bring reset low if the analog or digital supplies drop below the recommended operating condition to prevent power glitch related issues.
ds679a2 41 cs42l51 4.9 recommended power-down sequence to minimize audible pops when turning off or placing the codec in standby, 1. mute the dac?s & adc?s. 2. set the pdn bit in the power cont rol register to ?1?b. the codec will not power do wn until it reaches a fully muted sate. 3. bring reset low. adc initialization dac initialization software mode registers setup to desired settings. reset = low? no power 1. no audio signal generated. off mode (power applied) 1. no audio signal generated. 2. control port registers reset to default. control port active control port valid write seq. within 10 ms? hardware mode minimal feature set support. pdn bit = '1'b? sub-clocks applied 1. lrck valid. 2. sclk valid. 3. audio samples processed. valid mclk/lrck ratio? no yes no yes no yes yes no normal operation audio signal generated per control port or stand- alone settings. analog output freeze 1. aout bias = last audio sample. 2. dac modulators stop operation. 3. audible pops. error: mclk removed pdn bit set to '1'b (software mode only) standby mode 1. no audio signal generated. 2. control port registers retain settings. reset transition 1. pops suppressed. power off transition 1. audible pops. error: power removed valid mclk applied? no 20 ms delay charge caps 1. vq charged to quiescent voltage. 2. filtx+ charged. 2048 internal mclk cycle delay digital/analog output muted 50 ms delay charge pump powered up headphone amp powered up 20 s delay headphone amp powered down 20 s delay (dac only) stand-by transition 1. pops suppressed. error: mclk/lrck ratio change reset = low figure 23. initialization flow chart
42 ds679a2 cs42l51 4.10 software mode the control port is used to access the registers allowing the codec to be configured for the desired oper- ational modes and formats. the operation of the contro l port may be completely asynchronous with respect to the audio sample rates. however, to avoid potential interference problems, the control port pins should remain static if no operation is required. the control port operates in 2 modes: spi and i2c, with the codec acting as a slave device. spi mode is selected if there is a high-to-low transition on the ad0/cs pin after the reset pin has been brought high. i2c mode is selected by connecting the ad0/cs pin through a resistor to vl or dgnd, thereby permanently selecting the desired ad0 bit address state. 4.10.1 spi control in spi mode, cs is the cs42l51 chip select signal, cclk is the c ontrol port bit clock (input into the cs42l51 from the microcontroller), cdin is the input da ta line from the microcontr oller. data is clocked in on the rising edge of cclk. the codec will only support write operations. read request will be ig- nored. figure 24 shows the operation of the control port in spi mode. to write to a register, bring cs low. the first seven bits on cdin form the chip address and mu st be 1001010. the eighth bit is a read/write indi- cator (r/w ), which should be low to write. the next eight bits form the memory address pointer (map), which is set to the address of the register that is to be updated. the next eight bits are the data which will be placed into the regist er designated by the map. there is map auto increm ent capability, enabled by the incr bit in the map register. if incr is a zero, the map will stay constant fo r successive read or writes. if incr is set to a 1, the map will autoincrement after each byte is read or wr itten, allowing block reads or writes of successive registers. 4.10.2 i2c control in i2c mode, sda is a bidirectional da ta line. data is clocke d into and out of the pa rt by the clock, scl. there is no cs pin. pin ad0 forms the least significant bit of the chip address and should be connected through a resistor to vl or dgnd as desire d. the state of the pin is sensed while the cs42l51 is being reset. the signal timings for a read and write cycle are shown in figure 25 and figure 26 . a start condition is defined as a falling transition of sda while the clock is high. a stop condition is a rising transition while the clock is high. all other transitions of sda occur while the clock is low. th e first byte sent to the cs42l51 after a start condition consists of a 7 bit chip address field and a r/w bit (high for a read, low for a write). the upper 6 bits of the 7-bit address field are fixed at 100101. to communicate with a cs42l51 , the chip address field, which is the first byte sent to the cs42l51 , should match 100101 followed by the setting of the ad0 pin. the eighth bit of the address is the r/w bit. if the operation is a wr ite, the next byte is the memory address pointer (map) which selects the register to be read or written. if the operation is a read, 4 5 6 7 cclk chip address (write) map byte data 1 0 0 1 0 1 0 0 cdin incr 6 5 4 3 2 1 0 7 6 1 0 0 1 2 3 8 9 12 16 17 10 11 13 14 15 data +n cs 7 6 1 0 figure 24. control port timing in spi mode
ds679a2 43 cs42l51 the contents of the register pointe d to by the map will be output. setting the auto increment bit in map allows successive reads or writes of consecutive registers. each byte is separated by an acknowledge bit. the ack bit is output from the cs42l51 after each input byte is read, and is input to the cs42l51 from the microcontroller after each transmitted byte. since the read operation can not set the map, an aborted write operation is used as a preamble. as shown in figure 26 , the write operation is aborted after the acknowledge for the map byte by sending a stop condition. the following pseudocode illustrate s an aborted write operatio n followed by a read oper- ation. send start condition. send 100101x0 (chip address & write operation). receive acknowledge bit. send map byte, auto increment off. receive acknowledge bit. send stop condition, aborting write. send start condition. send 100101x1(chip address & read operation). receive acknowledge bit. receive byte, contents of selected register. send acknowledge bit. send stop condition. setting the auto increment bit in th e map allows successive reads or wr ites of consecutiv e registers. each byte is separated by an acknowledge bit. 4 5 6 7 24 25 scl chip address (write) map byte data data +1 start ack stop ack ack ack 1 0 0 1 0 1 ad0 0 sda incr 6 5 4 3 2 1 0 7 6 1 0 7 6 1 0 7 6 1 0 0 1 2 3 8 9 12 16 17 18 19 10 11 13 14 15 27 28 26 data +n figure 25. control port timing, i2c write scl chip address (write) map byte data data +1 start ack stop ack ack ack 1 0 0 1 0 1 ad0 0 sda 1 0 0 1 0 1 ad0 1 chip address (read) start incr 6 5 4 3 2 1 0 7 0 7 0 7 0 no 16 8 9 12 13 14 15 4 5 6 7 0 1 20 21 22 23 24 26 27 28 2 3 10 11 17 18 19 25 ack data + n stop figure 26. control port timing, i2c read
44 ds679a2 cs42l51 4.10.3 memory addr ess pointer (map) the map byte comes after the address byte and select s the register to be read or written. refer to the pseudo code above for implementation details. 4.10.3.1 map increment (incr) the device has map auto increment ca pability enabled by the incr bit (t he msb) of the map. if incr is set to 0, map will stay constant for successive i2c writes or reads and spi writes. if incr is set to 1, map will auto increment after each byte is written, allowing block reads or writes of successive registers.
ds679a2 45 cs42l51 5. register qu ick reference software mode register defaults are as shown. ?res erved? registers must main tain their default state. addrfunction7 6543210 01h id. chip_id4 chip_id3 chip_id2 chip_id1 chip_id0 rev_id2 rev_id1 rev_id0 p47 . default1 1011000 02h power ctl. 1. reserved pdn_dacb pdn_da ca pdn_pgab pdn_pgaa pdn_adcb pdn_adca pdn p47 . default0 0000000 03h speed ctl. & power ctl. 2. auto speed1 speed0 3-st_sp pdn_micb pdn_mica pdn_ micbias mclkdiv2 p48 . default1 0101110 04h interface ctl. sdout->sdin m/s dac_dif2 dac_dif1 dac_dif0 adc_i2s/lj digmix micmix p49 . default0 0000000 05h mic control & misc. adc_sngvol adcb_ dboost adca_ dboost micbias_ sel micbias_ lvl1 micbias_ lvl0 micb_ boost mica_ boost p51 . default0 0000000 06h adc control. adcb_hpf en adcb_hp frz adca_hpf en adca_hp frz softb zcrossb softa zcrossa p52 . default1 0100000 07h adc input select. , invert, mute. ainb_mux1 ainb_mux 0 aina_mux1 aina_mux0 inv_adcb inv_adca adcb_ mute adca_ mute p53 . default0 0000000 08h dac output control. hp_gain2 hp_gain1 hp_gain0 dac_sng vol inv_dacb inv_daca dacb_ mute daca_ mute p54 . default0 1100000 09h dac control. data_sel1 data_sel0 freez e reserved deemph reserved dac_szc1 dac_szc0 p55 . default0 0000110 0ah alca szc & pgaa vol- ume. alca_sr dis alca_zc dis reserved pgaa vol4 pgaa vol3 pgaa vol2 pgaa vol1 pgaa vol0 p56 . default0 0000000 0bh alcb szc & pgab vol- ume . alcb_sr dis alcb_zc dis reserved pgab vol4 pgab vol3 pgab vol2 pgab vol1 pgab vol0 p56 . default0 0000000 0ch adca atten- uator. adca_att7 adca_att 6 adca_att5 adca_att4 adca_att3 adca_att2 adca_att1 adca_att0 p57 . default0 0000000 0dh adcb atten- uator . adcb_att7 adcb_att 6 adcb_att5 adcb_att4 adcb_att3 adcb_att2 adcb_att1 adcb_att0 p57 . default0 0000000 0eh vol. control adcmixa. mute_adc mixa adcmixa vol6 adcmixa vol5 adcmixa vol4 adcmixa vol3 adcmixa vol2 adcmixa vol1 adcmixa vol0 p58 . default1 0000000 0fh vol. control adcmixb. mute_adc mixb adcmixb vol6 adcmixb vol5 adcmixb vol4 adcmixb vol3 adcmixb vol2 adcmixb vol1 adcmixb vol0 p58 . default1 0000000 10h vol. control pcmmixa. mute_pcm mixa pcmmixa vol6 pcmmixa vol5 pcmmixa vol4 pcmmixa vol3 pcmmixa vol2 pcmmixa vol1 pcmmixa vol0 p59 . default1 0000000 11h vol. control pcmmixb. mute_pcm mixb pcmmixb vol6 pcmmixb vol5 pcmmixb vol4 pcmmixb vol3 pcmmixb vol2 pcmmixb vol1 pcmmixb vol0 p59 . default1 0000000
46 ds679a2 cs42l51 12h beep freq. & ontime . freq3 freq2 freq1 freq0 ontime3 ontime2 ontime1 ontime0 p60 . default 0 0 0 0 0 0 0 0 13h beep off time & vol. offtime2 offtime1 offtime0 bpvol4 bpvol3 bpvol2 bpvol1 bpvol0 p61 . default 0 0 0 0 0 0 0 0 14h beep con- trol & tone config. repeat beep reserved treb_cf1 tr eb_cf0 bass_cf1 bass_cf0 tc_en p62 . default 0 0 0 0 0 0 0 0 15h tone control. treb3 treb2 treb1 treb0 bass3 bass2 bass1 bass0 p63 . default 1 0 0 0 1 0 0 0 16h vol. control aouta. aouta_ vol7 aouta_ vol6 aouta_ vol5 aouta_ vol4 aouta_ vol3 aouta_ vol2 aouta_ vol1 aouta_ vol0 p64 . default 0 0 0 0 0 0 0 0 17h vol. control aoutb. aoutb_ vol7 aoutb_ vol6 aoutb_ vol5 aoutb_ vol4 aoutb_ vol3 aoutb_ vol2 aoutb_ vol1 aoutb_ vol0 p64 . default 0 0 0 0 0 0 0 0 18h pcm & adc channel mixer. pcma1 pcma0 pcmb1 pcmb0 adca1 adca0 adcb1 adcb0 p64 . default 0 0 0 0 0 0 0 0 19h limiter threshold & szc disable. max2 max1 max0 cush2 cush1 cush0 lim_srdis lim_zcdis p65 . default 0 0 0 0 0 0 0 0 1ah limiter con- fig & release rate. limit_en limit_all lim_rrate 5 lim_rrate 4 lim_rrate 3 lim_rrate 2 lim_rrate 1 lim_rrate 0 p66 . default 0 1 0 0 0 0 0 0 1bh limiter attack rate. reserved reserved lim_arate5 lim_arate4 lim_arate3 lim_arate2 lim_arate1 lim_arate0 p67 . default 0 0 0 0 0 0 0 0 1ch alc enable & attack rate. alc_enb alc_ena alc_arate 5 aalc_rate 4 alc_arate 3 alc_arate 2 alc_arate 1 alc_arate 0 p67 . default 0 0 0 0 0 0 0 0 1dh alc release rate. reserved reserved alc_rrate 5 alc_rrate 4 alc_rrate 3 alc_rrate 2 alc_rrate 1 alc_rrate 0 p68 . default 0 0 0 0 0 0 0 0 1eh alc thresh- old. max2 max1 max0 min2 min1 min0 reserved reserved p69 . default 0 0 0 0 0 0 0 0 1fh noise gate config. ng_all ng_en ng_boost thresh2 thresh1 thresh0 ngdelay1 ngdelay0 p70 . default 0 0 0 0 0 0 0 0 20h status. reserved sp_clker r speb_ovfl spea_ovfl pcma_ovfl pcmb_ovfl adca_ovfl adcb_ovfl p71 . default 0 0 0 0 0 0 0 0 21h charge pump frequency. chrg_freq3 chrg_ freq2 chrg_ freq1 chrg_ freq0 reserved reserved reserved reserved p71 . default 0 1 0 1 0 0 0 0 addrfunction7 6543210
ds679a2 47 cs42l51 6. register description all registers are read/write except for the chip i.d. and revision register and interrupt status register which are read only. see the following bit definition tables for bit assi gnment information. the default state of each bit after a power-up sequence or reset is lis ted in each bit description. all ?reserved? registers must maintain their default state. note: certain functions are only available when the ?signal processing engine to dac? option is selected using the data_sel[1:0] bits, as described in section ?dac data selection (data_sel[1:0])? on page 55 . 6.1 chip i.d. and revision regist er (address 01h) (read only) chip i.d. (chip_id[4:0]) default: 11011 function: i.d. code for the cs42l51. permanently set to 11011. chip revision (rev_id[2:0]) default: 000 function: cs42l51 revision level. revi sion a is coded as 000. 6.2 power control 1 (address 02h) notes: 1. to activate the power down sequence for individual channels (a or b) both channels must first be pow- ered down either by enabling the pdn bit or by enabling the power down bits for both channels. en- abling the power down bit on an individual channel basis afte r the codec has fu lly powered up, will mute the selected channel without achieving any power savings. recommended channel power down sequence : (1) enable the pdn bit, (2) en able power down for the se- lect channels, (2) disable the pdn bit. power down dac x (pdn_dacx) default: 0 0 - disable 1 - enable function: dac channel x will either enter a power down or muted state when this bit is enabled. see note 1 above. 76543210 chip_id4 chip_id3 chip_id2 chip_id1 chip_id0 rev_id2 rev_id1 rev_id0 76543210 reserved pdn_dacb pdn_daca pdn_pgab pdn_pgaa pdn_adcb pdn_adca pdn
48 ds679a2 cs42l51 power down pga x (pdn_pgax) default: 0 0 - disable 1 - enable function: pga channel x will either enter a power down or mu ted state when this bit is enabled. see note 1 on page 47 . this bit is used in conjunction with ainx_mux bits to determine the analog input path to the adc. refer to ?adcx input select bits (a inx_mux[1:0])? on page 53 for the required settings. power down adc x (pdn_adcx) default: 0 0 - disable 1 - enable function: adc channel x will either en ter a power down or muted state wh en this bit is enabled. see note 1 on page 47 . power down (pdn) default: 0 0 - disable 1 - enable function: the entire codec will enter a low-power state when this function is enab led. the contents of the control port registers are retained in this mode. 6.3 mic power control & speed control (address 03h) auto-detect speed mode (auto) default: 1 0 - disable 1 - enable function: enables the auto-detect circuitry fo r detecting the speed mode of the codec when operating as a slave. when auto is enabled, the mclk/lrck ra tio must be implemented according to table 3 on page 37 . the speed[1:0] bits are ignored when this bit is enabled. speed is determined by th e mclk/lrck ratio. speed mode (speed[1:0]) default: 01 11 - quarter-speed mode (qsm) - 4 to 12.5 khz sample rates 10 - half-speed mode (hsm) - 12.5 to 25 khz sample rates 01 - single-speed mode (ssm) - 4 to 50 khz sample rates 00 - double-speed mode (dsm) - 50 to 100 khz sample rates function: sets the appropriate speed mode for the codec in mast er or slave mode. qsm is optimized for 8 khz sam- ple rate and hsm is optimized for 16 khz sample rate. these bits are ignored when the auto bit is enabled (see auto-detect speed mode (auto) above). 76543210 auto speed1 speed0 3-st_sp pdn_micb pdn_mica pdn_micbias mclkdiv2
ds679a2 49 cs42l51 tri-state serial port interface (3st_sp) d efault: 0 0 - disable 1 - enable function: when enabled, and the device is co nfigured as a master, then all serial port interface signals will be placed in a high-impedance output state. if the serial port interface is configured as a slave, only the sdout pin will be placed in a high-im pedance state. the other sign als will remain as inputs. power down mic x (pdn_micx) default: 1 0 - disable 1 - enable function: when enabled, the micr ophone pre-amplifier for channel x will be in a power down state. power down mic bias (pdn_micbias) default: 1 0 - disable 1 - enable function: when enabled, the microph one bias circuit will be in a power down state. mclk divide by 2 (mclkdiv2) default: 0 0 - disabled 1 - divide by 2 function: divides the input mclk by 2 prior to all internal circui try. this bit is ignored when the auto bit is disabled in slave mode. 6.4 interface cont rol (address 04h) sdout to sdin loopback (sdout->sdin) default: 0 0 - disabled; sdout internally disconnected from sdin 1 - enabled; sdout internally connected to sdin function: internally loops the signal on the sdout pin to sdin. master/slave mode (m/s ) default: 0 0 - slave 1 - master function : selects either master or slave operation for the serial port. 76543210 sdout->sdin m/s dac_dif2 dac_dif1 dac_dif0 adc_i2s/lj digmix micmix
50 ds679a2 cs42l51 dac digital interface format (dac_dif[2:0]) default = 000 function: selects the digital interface format used for the data in on sdin. the required relationship between the left/right clock, serial clock and se rial data is defined by the digital interface format and the options are detailed in the section ?digital interface formats? on page 39 . adc i2s or left-justified (adc_i2s/lj ) default: 0 0 - left-justified 1 - i2s function: selects either the i2s or left-justified digital interfac e format for the data on sdout. the required relation- ship between the left/right clock, seri al clock and serial data is defined by the digital interface format and the options are detailed in the section ?digital interface formats? on page 39 . digital mix (digmix) default: 0 function: selects between the adc or a digital mix of the adc and dac into the serial port to the sdout pin. this mix function is affected by the da ta select bits data_sel[1:0]. microphone mix (micmix) default: 0 0 - disabled; no mix: left/right channel to adc serial port, sdout. 1 - enabled; mix: differential mix ((a-b)/2)to adc serial port, sdout. function: selects between the adc stereo mix or a di fferential mix of analog inputs a and b. dac_dif[2:0] description figure 000 left justified, up to 24-bit data 21 on page 39 001 i2s, up to 24-bit data 20 on page 39 010 right justifie d, 24-bit data 22 on page 39 011 right justified, 20-bit data 22 on page 39 100 right justifie d, 18-bit data 22 on page 39 101 right justifie d, 16-bit data 22 on page 39 110 reserved - 100 reserved - digmix data_sel[1:0] mix selected 0 xx no mix: adc to adc serial port, sdout data. 1 00 no mix: sdin data to adc serial port, sdout data. 01 mix: adc + sdin data to adc serial port, sdout data. 10 no mix: adc to adc serial port, sdout data. 11 reserved
ds679a2 51 cs42l51 6.5 mic control (address 05h) adc single volume control (adc_sngvol) default: 0 0 - disabled 1 - enabled function: the individual pga volume (pgax_ volx) and adc channel attenuation (adcx_attx) levels are indepen- dently controlled by their respective control registers wh en this function is disabled. when enabled, the vol- ume on both channels is determined by the adca attenuator co ntrol register, or the pgaa control register, and the adcb attenuator and pgab control registers are ignored. adcx 20db digital boost (adcx_dboost) default: 0 0 - disabled 1 - enabled function: applies a 20db digital gain to the input signal on adc channel x, regardless of the input path. mic bias select (micbias_sel) default: 0 0 - micbias on ai n3b/micin2 pin 1 - micbias on ain2b pin function: determines the output pin for the in ternally generated micbias signal. if set to ?0?b, then the micbias is output on the ain3b/micin2 pin. if set to ?1?b, then the micbi as is output on the ain2b pin. mic bias level (micbias_lvl[1:0]) default: 00 00 - 0.8 x va 01 - 0.7 x va 10 - 0.6 x va 11 - 0.5 x va function: determines the output voltage level of the micbias output. mic x preamplifier boost (micx_boost) default: 0 0 - +16 db gain 1 - +32 db gain function: determines the amount of gain applied to the microphone preamplifier for channel x. 76543210 adc_sngvol adcb_dboost adca_dboost micbias_sel mi cbias_lvl1 micbias_lvl0 micb_boost mica_boost
52 ds679a2 cs42l51 6.6 adc control (address 06h) adcx high-pass filter enable (adcx_hpfen) default: 1 0 - high-pass filter is disabled 1 - high-pass filter is enabled function: when this bit is set, the internal high -pass filter will be enabled for adcx. when set to ?0?, the high-pass filter will be disabled. for dc measurements, this bit must be cleared to ?0?. see ?adc digital filter characteris- tics? on page 15. adcx high-pass filter freeze (adcx_hpfrz) default: 0 0 - continuous dc subtraction 1 - frozen dc subtraction function: the high-pass filter works by continuously subtracting a measure of the dc offset from the output of the decimation filter. if the adcx_hpfrz bit is taken high during normal operation, the current value of the dc offset is frozen and this dc offs et will continue to be subtracted fr om the conversion result. for dc mea- surements, this bit must be set to ?1?. see ?adc digital filter characteristics? on page 15. soft ramp chx control (softx) def ault: 0 0 - disabled 1 - enabled function: soft ramp allows level changes to be implemented via an incremental ramp. adcx_att[7:0] digital atten- uation changes are ramped from the current level to the new level at a rate of 0.125 db per lrck period. pgax_vol[4:0] gain changes are ramped in 0.5 db steps every 16 lrck periods. soft ramp & zero cross enabled when used in conjunction with the zcrossx bit, the pgax_vol[4:0] gain changes will occur in 0.5 db steps and be implemented on a signal zero crossing. zero cross chx control (zcrossx) default: 0 0 - disabled 1 - enabled function: zero cross enable dictates that sign al level changes will occur on a signal zero crossing to minimize audible artifacts. the requested level change will occur after a timeout period of 1024 sample perio ds (approximate- ly 10.7 ms at 48 khz sample rate) if the signal does no t encounter a zero crossing. the zero cross function is independently monitored and implemented for each channel. soft ramp & zero cross enabled when used in conjunction with the softx bit, the pgax_vol[4:0] gain changes will occur in 0.5 db steps and be implemented on a signal zero crossing. the adc attenuator adcx_att[7:0] is not affected by the zcrossx bit. 76543210 adcb_hpfen adcb_hpfrz adca_hpfen a dca_hpfrz softb zcrossb softa zcrossa
ds679a2 53 cs42l51 6.7 adcx input select, inve rt & mute (address 07h) adcx input select bi ts (ainx_mux[1:0]) default: 00 function: selects the specified analog input signal into adcx. the microphone pre-amplifier is only available when pdn_pgax is disabled. see figure 27. softx zcrossx analog pga volume (pgax_vol[4:0]) digital attenuator (adcx_att[7:0]) 00 volume changes immediately. volume changes immediately. 01 volume changes at next zero cross time. volume changes immediately. 10 volume changes in 0.5 db steps. change volume in 0.125 db steps. 11 volume changes in 0.5 db steps at every signal zero-cross. change volume in 0.125 db steps. 76543210 ainb_mux1 ainb_mux0 aina_mux1 aina_mux0 inv_adcb inv_adca adcb_mute adca_mute pdn_pgax ainx_mux[1:0] selected path to adc 000 ain1x-->pgax 001 ain2x-->pgax 010 ain3x/micinx-->pgax 011 ain3x/micinx-->pre-amp (+16/+32 db gain) -->pgax 100 ain1x 101 ain2x 110 ain3x/micinx 111 reserved mux ain1x ain2x ain3x / micinx pga +16/ 32 db mux ainx_mux[1:0] pdn_pgax ain1x ain2x ain3x decoder adc figure 27. ain & pga selection
54 ds679a2 cs42l51 adcx invert signal polarity (inv_adcx) default: 0 0 - disabled 1 - enabled function: when enabled, this bit will invert the signal polarity of the adc x channel. adcx channel mute (adcx_mute) default: 0 0 - disabled 1 - enabled function: the output of chann el x adc will mute when enabled. the muting function is affected by the adcx soft bit (soft). 6.8 dac output c ontrol (address 08h) headphone analog gain (hp_gain[2:0]) default: 011 function: these bits select the gain multiplie r for the headphone/line outputs. see ?line output voltage characteris- tics? on page 18 and ?headphone output power characteristics? on page 19 . dac single volume control (dac_sngvol) default: 0 function: the individual channel volume levels are independently controlled by th eir respective volume control reg- isters when this function is disabled. when enabled, the volume on all channels is determined by the aou- ta volume control register and the aoutb volume control register is ignored. 76543210 hp_gain2 hp_gain1 hp _gain0 dac_sngvo l inv_pcmb inv_pcma da cb_mute daca_mute hp_gain[2:0] gain setting 000 0.3959 001 0.4571 010 0.5111 011 0.6047 100 0.7099 101 0.8399 110 1.000 111 1.1430
ds679a2 55 cs42l51 pcmx invert signal polarity (inv_pcmx) default: 0 0 - disabled 1 - enabled function: when enabled, this bit will invert the signal polarity of the pcm x channel. dacx channel mute (dacx_mute) default: 0 0 - disabled 1 - enabled function: the output of channel x dac will mute when enabled. the muti ng function is affected by the dacx soft and zero cross bits (dacx_szc[1:0]). 6.9 dac control (address 09h) dac data selection (data_sel[1:0]) default: 00 00 - pcm serial port to dac 01 - signal processing engine to dac 10 - adc serial port to dac 11 - reserved function : selects the digital signal source for the dac. note : certain functions are only available when the ?signal processing engine to dac? option is selected using these bits. freeze controls (freeze) default: 0 function: this function will freeze the previous settings of, and allow modifications to be made to all control port reg- isters without the changes taking effe ct until the freeze is disabled. to have multiple changes in the con- trol port registers take effect simultaneously, en able the freeze bit, make all register changes, then disable the freeze bit. dac de-emphasis control (deemph) default: 0 0 - no de-emphasis 1 - de-emphasis enabled function: note: the data_sel[1:0] bits in reg09h must be set to ?01?b to enable function control. enables the digital filter to apply the standard 15 s/50 s digital de-emphasis filter response for a sample rate of 44.1 khz. 76543210 data_sel1 data_sel0 freeze reserve d deemph reserved dac_szc1 dac_szc0
56 ds679a2 cs42l51 dac soft ramp and zero cr oss control (dac_szc[1:0]) default = 01 00 - immediate change 01 - zero cross 10 - soft ramp 11 - soft ramp on zero crossings function: note: the data_sel[1:0] bits in reg09h must be set to ?01?b to enable function control immediate change when immediate change is selected all volume level changes will take effect immediately in one step. zero cross this setting dictates that signal level changes, either by gain changes, attenuation changes or muting, will occur on a signal zero crossing to minimize audible artifacts. the requ ested level change will occur after a timeout period between 1024 and 2048 sample periods ( 21.3 ms to 42.7 ms at 48 khz sample rate) if the signal does not encounter a zero crossing. the zero cross function is independently monitored and imple- mented for each channel. note : the lim_srdis bit is ignored. soft ramp soft ramp allows level changes, either by gain change s, attenuation changes or muting, to be implemented by incrementally ramping, in 1/8 db steps, from the cu rrent level to the new level at a rate of 0.5 db per 4 left/right clock periods. soft ramp on zero crossing this setting dictates that signal level changes, either by gain changes, attenuation changes or muting, will occur in 1/8 db steps and be impl emented on a signal zero crossing . the 1/8 db level change will occur after a timeout period between 512 and 1024 sample perio ds (10.7 ms to 21.3 ms at 48 khz sample rate) if the signal does not encounter a zero crossing. the ze ro cross function is independently monitored and im- plemented for each channel. note : the lim_srdis bit is ignored. 6.10 alcx & pgax control: alca, pgaa (address 0ah) & al cb, pgab (address 0bh) alcx soft ramp disable (alcx_srdis) default: 0 0 - off 1 - on function: overrides the softx bit setting for the adc. when this bi t is set, the alc attack rate in the pga will not be dictated by the soft ramp setting. alc volu me level changes will take effect in one step. 76543210 alcx_srdis alcx_zcdis reserved pgax_vo l4 pgax_vol3 pgax_vol2 pgax_vol1 pgax_vol0
ds679a2 57 cs42l51 alcx zero cross disable (alcx_zcdis) default: 0 0 - off 1 - on function: overrides the zcrossx bit setting for th e adc. when this bit is set, the alc attack rate in the pga will not be dictated by the zero cross settin g. alc volume level changes will take effect immediately in one step. pga x gain control (pgax_vol[4:0]) default: 00000 function: the pgax gain control regist er allows independent setting of the signal levels in 0.5 db increments as dic- tated by the adcx soft and zero cross bits (softx & zcrossx) from +12 db to -3 db. gain settings are decoded as shown in the table above. the gain changes are implemented as dictated by the alcx soft & zero cross bits (alcx_szc). levels are decoded as described in the table above. note: when the alc is enabled the pga is automatically controlled and should not be adjusted manually. 6.11 adcx attenuator: adca (address 0ch) & adcb (address 0dh) adcx attenuation cont rol (adcx_att[7:0]) default: 00h function: the level of adcx can be adjusted in 1.0 db incremen ts as dictated by the adcx soft and zero cross bits binary code volume setting 11000 +12 db 01010 +5 db 00000 0 db 11111 -0.5 db 11110 -1 db 11010 -3 db 76543210 adcx_att7 adcx_att6 adcx_att5 adcx_att4 adcx_att3 adcx_att2 adcx_att1 adcx_att0 binary code volume setting 0111 1111 0 db 0000 0000 0 db 1111 1111 -1 db 1111 1110 -2 db 1010 0000 -96 db 1000 0000 -96 db
58 ds679a2 cs42l51 (softx & zcrossx) from 0 to -96 db. levels are decod ed in two?s complement, as shown in the table above. note: when the alc is enabled the attenuator and pga volume is automatically controlled and should not be adjusted manually. 6.12 adcx mixer volume control: adca (address 0eh) & adcb (address 0fh) note: the data_sel[1:0] bits in reg09h mu st be set to ?01?b to enable f unction control in this register. adcx mixer channel mute (mute_adcmixx) default: 1 0 - disabled 1 - enabled function: the adc channel x input to the output mixer will mute when enabled. the muting function is affected by the dacx soft and zero cr oss bits (dacx_szc[1:0]). adcx mixer volume control (adcmixx_vol[6:0]) default = 000 0000 function: the level of the adcx input to the output mixer can be adjusted in 0.5 db increments as dictated by the dacx soft and zero cross bits (dacx_szc[1:0]) from +12 to -51.5 db. levels are decoded as shown in the table above. 7 6543210 mute_adcmixx adcmixx_vol6 adcmixx_vol5 adcmixx_vol4 adcmixx_vol3 adcmixx_vol2 adcmixx_vol1 adcmixx_vol0 binary code volume setting 001 1000 +12.0 db 000 0000 0 db 111 1111 -0.5 db 111 1110 -1.0 db 001 1001 -51.5 db
ds679a2 59 cs42l51 6.13 pcmx mixer volume control: pcma (address 10h) & pcmb (address 11h) note: the data_sel[1:0] bits in reg09h must be set to ?0 1?b to enable function c ontrol in this register. pcmx mixer channel mute (mute_pcmmixx) default = 1 0 - disabled 1 - enabled function: the pcm channel x input to the output mixer will mute when enabled. the muting function is affected by the dacx soft and zero cross bits (dacx_szc[1:0]). pcmx mixer volume cont rol (pcmmixx_vol[6:0]) default: 000 0000 function: the level of the pcmx input to the output mixer can be adjusted in 0.5 db increments as dictated by the dacx soft and zero cross bits (d acx_szc[1:0]) from +12 to -51.5 db . levels are decoded as described in the table above. 7 6543210 mute_pcmmixx pcmmixx_vol 6 pcmmixx_vol 5 pcmmixx_vol 4 pcmmixx_vol 3 pcmmixx_vol 2 pcmmixx_vol 1 pcmmixx_vol 0 binary code volume setting 001 1000 +12.0 db 000 0000 0 db 111 1111 -0.5 db 111 1110 -1.0 db 001 1001 -51.5 db
60 ds679a2 cs42l51 6.14 beep frequency & timi ng configuration (address 12h) note: the data_sel[1:0] bits in reg09h must be set to ?01?b to enable f unction control in this register. beep frequency (freq[3:0]) default: 0000 function: the frequency of the beep signal can be adjuste d from 260.87 hz to 2181. 82 hz. beep frequency will scale directly with sample rate, fs, but is fixed at the nominal fs within each speed mode. refer to figure 16 on page 34 for single, multiple a nd continuous beep conf igurations using the repeat and beep bits. beep on time duration (ontime[3:0]) default: 00h function: the on-duration of the beep signal can be adjusted from approximately 86 ms to 5.2 s. the on-duration will scale inversely with sample rate, fs , but is fixed at the nominal fs wit hin each speed mode. refer to figure 16 on page 34 for single, multiple and continuous be ep configurations using the repeat and beep bits. 76543210 freq3 freq2 freq1 freq0 ontime3 ontime2 ontime1 ontime0 freq[3:0] frequency fs = 12, 24, 48 or 96 khz pitch 0000 260.87 hz c4 0001 521.74 hz c5 0010 585.37 hz d5 0011 666.67 hz e5 0100 705.88 hz f5 0101 774.19 hz g5 0110 888.89 hz a5 0111 1000.00 hz b5 1000 1043.48 hz c6 1001 1200.00 hz d6 1010 1333.33 hz e6 1011 1411.76 hz f6 1100 1600.00 hz g6 1101 1714.29 hz a6 1110 2000.00 hz b6 1111 2181.82 hz c7 time[3:0] on time fs = 12, 24, 48 or 96 khz 0000 86 ms 1111 5.2 s
ds679a2 61 cs42l51 6.15 beep off time & volume (address 13h) note: the data_sel[1:0] bits in reg09h must be set to ?0 1?b to enable function c ontrol in this register. beep off time (offtime[2:0]) default: 0 function: the off-duration of the beep signal can be adjusted fr om approximately 75 ms to 680 ms. the off-duration will scale inversely with samp le rate, fs, but is fixed at the nomi nal fs within each speed mode. refer to figure 16 on page 34 fo r single, multiple and c ontinuous beep configurati ons using the repeat and beep bits. beep volume (bpvol[4:0]) default: 00000 function: the level of the beep into the output mixer can be adjusted in 2.0 db increments from +12 db to -50 db. refer to figure 16 on p age 34 for single, multiple and continuous beep conf igurations using the repeat and beep bits. levels ar e decoded as described in the table above. 76543210 offtime2 offtime1 offtime0 bpvol4 bpvol3 bpvol2 bpvol1 bpvol0 offtime[2:0] off time fs = 12, 24, 48 or 96 khz 000 1.23 s 001 2.58 s 010 3.90 s 011 5.20 s 100 6.60 s 101 8.05 s 110 9.35 s 111 10.80 s binary code volume setting 00110 +12.0 db 00000 0 db 11111 -2 db 11110 -4 db 00111 -50 db
62 ds679a2 cs42l51 6.16 beep configuration & tone configuration (address 14h) note: the data_sel[1:0] bits in reg09h mu st be set to ?01?b to enable f unction control in this register. repeat beep (repeat) default: 0 0 - disabled 1 - enabled function: this bit is used in conjun ction with the beep bit to mix a continuous or periodic beep wit h the analog output. refer to figure 16 on page 34 for a desc ription of each configuration option. beep (beep) default: 0 0 - disabled 1 - enabled function: this bit is used in conjunction with the repeat bit to mix a continuous or periodic beep wit h the analog output. note: re-engaging the beep be fore it has complete d its initial cycle will cause the beep signal to remain on for the maximum ontime duration. refer to figure 16 on page 34 for a description of each con- figuration option. treble corner frequency (treb_cf[1:0]) default: 00 00 - 5 khz 01 - 7 khz 10 - 10 khz 11 - 15 khz function: the treble corner frequency is user selectable as shown above. bass corner frequency (bass_cf[1:0]) default: 00 00 - 50 hz 01 - 100 hz 10 - 200 hz 11 - 250 hz function: the bass corner frequency is user selectable as shown above. tone control enable (tc_en) default = 0 0 - disabled 1 - enabled function: the bass and treble tone control features are active when this bit is enabled. 76543210 repeat beep reserved treb_cf1 treb_cf0 bass_cf1 bass_cf0 tc_en
ds679a2 63 cs42l51 6.17 tone control (address 15h) note: the data_sel[1:0] bits in reg09h must be set to ?0 1?b to enable function c ontrol in this register. treble gain level (treb[3:0]) default: 1000 db (no treble gain) function: the level of the shelving treble gain filter is set by treble gain level. the level can be adjusted in 1.5 db increments from +12.0 to -10.5 db. bass gain level (bass[3:0]) default: 1000 db (no bass gain) function: the level of the shelving bass gain filter is set by ba ss gain level. the level can be adjusted in 1.5 db in- crements from +10.5 to -10.5 db. 76543210 treb3 treb2 treb1 treb0 bass3 bass2 bass1 bass0 binary code gain setting 0000 +12.0 db 0111 +1.5 db 1000 0 db 1001 -1.5 db 1111 -10.5 db binary code gain setting 0000 +12.0 db 0111 +1.5 db 1000 0 db 1001 -1.5 db 1111 -10.5 db
64 ds679a2 cs42l51 6.18 aoutx volume control: aouta (address 16h) & aoutb (address 17h) note: the data_sel[1:0] bits in reg09h mu st be set to ?01?b to enable f unction control in this register. aoutx volume control (aoutx_vol[7:0]) default = 00h function: the level of the analog outputs can be adjusted in 0. 5 db increments as dictated by the dac soft and zero cross bits (dacx_szc[1:0]) from +12 to -102 db. leve ls are decoded as described in unsigned in the table above. note: when the limiter is enabled the aout volume is automatically co ntrolled and should not be adjust- ed manually. alternative volume control may be achieved using the pcmmixx_vol[6:0] bits. 6.19 adc & pcm channe l mixer (address 18h) note: the data_sel[1:0] bits in reg09h mu st be set to ?01?b to enable f unction control in this register. channel mixer (pcmx[1:0] & adcx[1:0]) default: 00 function: implements mono mixes of the left and right channels as well as a left/right channel swap. 76543210 aoutx_vol7 aoutx_vol6 aoutx_vol5 aoutx_vol4 aoutx_vol3 aoutx_vol2 aoutx_ vol1 aoutx_vol0 binary code volume setting 0001 1000 +12.0 db 0000 0000 0 db 1111 1111 -0.5 db 1111 1110 -1.0 db 0011 0100 -102 db 0001 1001 -102 db 76543210 pcma1 pcma0 pcmb1 pcmb0 adca1 adca0 adcb1 adcb0 pcma[1:0] and/or adca[1:0] aouta pcmb[1:0] and/or adcb[1:0] aoutb 00 l 00 r 01 01 10 10 11 r 11 l lr + 2 ------------ lr + 2 ------------
ds679a2 65 cs42l51 6.20 limiter threshold szc disable (address 19h) note: the data_sel[1:0] bits in reg09h must be set to ?0 1?b to enable function c ontrol in this register. maximum threshold (max[2:0]) default: 000 function: sets the maximum level, below fullscale , at which to limit and attenuate the output signal at the attack rate. bass, treble and digital gain settings that boost the signal beyond the maximum threshold may trigger an attack. cushion threshold (cush[2:0]) default: 000 function: sets a cushion level below fullscale . this setting is usually set sli ghtly below the maximum (max[2:0]) threshold. the limiter uses this cushion as a hysteresis point for the input signal as it maintains the signal below the maximum as well as below the cushion setting . this provides a more na tural sound as the limiter attacks and releases. 76543210 max2 max1 max0 cush2 cush1 cush0 lim_srdis lim_zcdis max[2:0] threshold setting (db) 000 0 001 -3 010 -6 011 -9 101 -12 101 -18 110 -24 111 -30 cush[2:0] threshold setting (db) 000 0 001 -3 010 -6 011 -9 101 -12 101 -18 110 -24 111 -30
66 ds679a2 cs42l51 limiter soft ramp disable (lim_srdis) default: 0 0 - off 1 - on function: overrides the dac_szc setting. when this bit is set, the limiter attack and release rate will not be dictated by the soft ramp setting. note: th is bit is ignored when the zero-cross function is enabled (i.e. when dac_szc[1:0] = ?01?b or ?11?b.) limiter zero cross disable (lim_zcdis) default: 0 0 - off 1 - on function: overrides the dac_szc setting. when this bit is set, the limiter attack & release rate will not be dictated by the zero cross setting. 6.21 limiter release rate register (address 1ah) note: the data_sel[1:0] bits in reg09h mu st be set to ?01?b to enable f unction control in this register. peak detect and limi ter enable (limit_en) default: 0 0 - disabled 1 - enabled function: limits the maximum signal amplitude to prevent clipping when this function is enabled. peak signal limiting is performed by digital attenuation. note: when the limiter is enabled the aout volume is automatically controlled and should not be adjusted manually. alte rnative volume control ma y be realized using the pcmmixx_vol[6:0] bits. peak signal limit all channels (limit_all) default: 1 0 - individual channel 1 - both channel a & b function: when set to 0, the peak signal limit er will limit the maximum si gnal amplitude to preven t clipping on the spe- cific channel indicating clipping. the ot her channels will not be affected. when set to 1, the peak signal limi ter will limit the maximum signal amp litude to prevent clipping on both channels in response to any single channel indicating clipping. 76543210 limit_en limit_all rrate5 rrate4 rrate3 rrate2 rrate1 rrate0
ds679a2 67 cs42l51 limiter release rate (rrate[5:0]) default: 111111 function: sets the rate at which the limiter releases the digita l attenuation from levels below the minimum setting in the limiter threshold register, and returns the anal og output level to the aoutx_vol[7:0] setting. the limiter release rate is user selectable but is also a function of the sampling frequency, fs, and the dac_szc setting unless the disable bit is enabled. 6.22 limiter attack rate register (address 1bh) note: the data_sel[1:0] bits in reg09h must be set to ?0 1?b to enable function c ontrol in this register. limiter attack rate (arate[5:0]) default: 000000 function: sets the rate at which the limiter attenuates the analog output from levels above the maximum setting in the limiter threshold register. the limiter attack rate is user-selectable but is al so a function of the samp ling frequency, fs, and the dac_szc setting unless the disable bit is enabled. 6.23 alc enable & atta ck rate (address 1ch) alc enable (alc_enx) default: 0 0 - disabled 1 - enabled function: enables automatic level co ntrol for adc channel x. note: when the alc is enabled, the attenuator and pga volume is automatically controlled and should not be adjusted manually. binary code release time 000000 fastest release 111111 slowest release 76543210 reserved reserved arate5 arate4 arate3 arate2 arate1 arate0 binary code attack time 000000 fastest attack 111111 slowest attack 76543210 alc_enb alc_ena alc_arate5 alc_arate4 alc_ arate3 alc_arate2 alc_arate1 alc_arate0
68 ds679a2 cs42l51 alc attack rate (arate[5:0]) default: 000000 function: sets the rate at which the alc attenuates the analog input from levels above the maximum setting in the alc threshold register. the limiter attack rate is user-selectable but is also a function of the sampling frequency, fs, and the softx & zcrossx bit settings unless the disa ble bit for each function is enabled. 6.24 alc release rate (address 1dh) alc release rate (rrate[5:0]) default: 111111 function: sets the rate at which the alc releases the pga & di gital attenuation from leve ls below the minimum setting in the alc threshold register, and returns the input level to the pga_vol[4:0] & adcx_att[7:0] setting. the alc release rate is user select able but is also a function of the sampling frequency, fs, and the softx & zcross bit settings unless the disable bit for each function is enabled. binary code attack time 000000 fastest attack 111111 slowest attack 76543210 reserved reserved alc_rrate5 alc_rrate4 alc_rrate3 alc_rrate2 alc_rrate1 alc_rrate0 binary code release time 000000 fastest release 111111 slowest release
ds679a2 69 cs42l51 6.25 alc threshold (address 1eh) maximum threshold (max[2:0]) default: 000 function: sets the maximum level, relative to full-scale, at which to limit and atte nuate the input signal at the attack rate. minimum threshold (min[2:0]) default: 000 function: sets the minimum level at which to disengage the alc?s attenuation or amplify the input signal at a rate set in the release rate register until levels again reach this minimum threshold. the alc uses this minimum as a hysteresis point for the input signal as it mainta ins the signal below the maximum as well as below the minimum setting. this provides a more natural sound as the alc attacks and releases. 76543210 max2 max1 max0 min2 min1 min0 reserved reserved max[2:0] threshold setting (db) 000 0 001 -3 010 -6 011 -9 100 -12 101 -18 110 -24 111 -30 min[2:0] threshold setting (db) 000 0 001 -3 010 -6 011 -9 100 -12 101 -18 110 -24 111 -30
70 ds679a2 cs42l51 6.26 noise gate configurat ion & misc. (a ddress 1fh) noise gate channel gang (ng_all) default: 0 0 - disabled 1 - enabled function : gangs the noise gate function for channel a and b. w hen enabled, both channels must fall below the thresh- old setting for the noise gate attenuation to take effect. noise gate en able (ng_en) default: 0 0 - disabled 1 - enabled function: enables the noise gate. maximum attenuation is relative to all gain settings applied. noise gate boost (ng_boost) and threshold (thresh[3:0]) default: 000 function: sets the threshold level of the noise gate. input signa ls below the threshold leve l will be attenuated to -96 db. ng_boost = ?1?b adds 30 db to the threshold settings. noise gate delay timing (ngdelay[1:0]) default: 00 00 - 50 ms 01 - 100 ms 10 - 150 ms 11 - 200 ms function: sets the delay time before the noise gate attacks. noise gate attenuation is dictated by the softx & zcross bit settings unless the disable bit for each function is enabled. 76543210 ng_all ng_en ng_boost thresh2 thr esh1 thresh0 ngdelay1 ngdelay0 thresh[2:0] minimum setting (ng_boost = ?0?b) minimum setting (ng_boost = ?1?b) 000 -64 db -34 db 001 -67 db -37 db 010 -70 db -40 db 011 -73 db -43 db 100 -76 db -46 db 101 -82 db -52 db 110 reserved -58 db 111 reserved -64 db
ds679a2 71 cs42l51 6.27 status (address 20h) (read only) for all bits in this register, a ?1? means the associated error condition has occurred at least once since the register was last read. a?0? means the associated erro r condition has not occurred since the last reading of the register. reading the register resets all bits to 0. serial port clock error (sp_clk error) default: x function: indicates an invalid mclk to lrck ratio. see ?serial port clocking? on page 37 for valid clock ratios. note: on initial power up and a pplication of clocks, this bit will be high as the serial po rt re-synchronizes. signal processing engine overflow (mixx_ovfl) default: x function: indicates a digital overflow condition within the data path after the signal processing engine. pcmx overflow (pcmx_ovfl) default: x function: indicates a digital overflow condition within the data path of the pcm mix. adc overflow (adcx_ovfl) default = x function: indicates that there is an over-range condition anywhe re in the cs42l51 adc signal path of each of the associated adc?s. 6.28 charge pump frequency (address 21h) charge pump frequency (chrg_freq[3:0]) default: 0101 function: alters the clocking frequency of the charge pump in 1/(n+2) fractions of the dac oversampling rate, 128fs, should the switching frequen cy interfere with other system frequencies such as th ose in the am radio band. note: distortion performance may be affected. 76543210 reserved sp_clkerr spea_ovfl speb_ovfl pcma _ovfl pcmb_ovfl adca_ovfl adcb_ovfl 76543210 chrg_freq 3 chrg_freq 2 chrg_freq 1 chrg_freq 0 reserved reserved reserved reserved n chrg_freq[3:0] frequency 00000 ... ... 15 1111 64 xfs n 2 + ---------------- -
72 ds679a2 cs42l51 7. analog performance plots 7.1 headphone thd+n versus output power plots test conditions (unless otherwise sp ecified): input test signal is a 997 hz sine wave; measurement band- width is 10 hz to 20 khz; fs = 48 khz. plots were ta ken from the cdb42l51 using an audio precision an- alyzer. g = 0.6047 g = 0.7099 g = 0.8399 g = 1.0000 g = 1.1430 legend -100 -10 -95 -90 -85 -80 -75 -70 -65 -60 -55 -50 -45 -40 -35 -30 -25 -20 -15 d b r a 0 80m 10m 20m 30m 40m 50m 60m 70m w figure 28. thd+n vs. ouput power per channel at 1.8 v (16 ? load) va_hp = va = 1.8 v note: graph shows the out- put power per channel (i.e. output power = 23 mw into single 16 ? and 46 mw into stereo 16 ? with thd+n = - 75 db). g = 0.6047 g = 0.7099 g = 0.8399 g = 1.0000 g = 1.1430 legend -100 -10 -95 -90 -85 -80 -75 -70 -65 -60 -55 -50 -45 -40 -35 -30 -25 -20 -15 d b r a 0 80m 10m 20m 30m 40m 50m 60m 70m w figure 29. thd+n vs. ouput power per channel at 2.5 v (16 ? load) va_hp = va = 2.5 v note: graph shows the out- put power per channel (i.e. output power = 44 mw into single 16 ? and 88 mw into stereo 16 ? with thd+n = - 75 db).
ds679a2 73 cs42l51 g = 0.6047 g = 0.7099 g = 0.8399 g = 1.0000 g = 1.1430 legend -100 -20 -95 -90 -85 -80 -75 -70 -65 -60 -55 -50 -45 -40 -35 -30 d b r a 0 60m 6m 12m 18m 24m 30m 36m 42m 48m 54m w figure 30. thd+n vs. ouput power per channel at 1.8 v (32 ? load) va_hp = va = 1.8 note: graph shows the out- put power per channel (i.e. output power = 22 mw into single 32 ? and 44 mw into stereo 32 ? with thd+n = - 75 db). g = 0.6047 g = 0.7099 g = 0.8399 g = 1.0000 g = 1.1430 legend -100 -20 -95 -90 -85 -80 -75 -70 -65 -60 -55 -50 -45 -40 -35 -30 -25 d b r a 0 60m 5m 10m 15m 20m 25m 30m 35m 40m 45m 50m 55m w figure 31. thd+n vs. ouput power per channel at 2.5 v (32 ? load) va_hp = va = 2.5 v note: graph shows the out- put power per channel (i.e. output power = 42 mw into single 32 ? and 84 mw into stereo 32 ? with thd+n = - 75 db).
74 ds679a2 cs42l51 7.2 adc_filt+ capacitor effects on thd+n the value of the capacitor on the adc_filt+ pin, 16, affects the low frequency total harmonic distortion + noise (thd+n) performance of the adc. larger capaci tor values yield significant improvement in thd+n at low frequencies. figure 32 shows the thd+n versus frequency for the adc analog input. plots were tak- en from the cdb42l51 using an audio precision analyzer. -100 - 60 -96 -92 -88 -84 -80 -76 -72 -68 -64 d b f s 20 20k 50 100 200 500 1k 2k 5k 10k hz figure 32. adc thd+n vs. fr equency w/capacitor effects 1 f legend ? capacitor value on adc_filt+ 10 f 22 f
ds679a2 75 cs42l51 8. example system clock frequencies 8.1 auto detect enabled *the ?mclkdiv2? pin 4 must be set hi. sample rate lrck (khz) mclk (mhz) 1024x 1536x 2048x* 3072x* 8 8.1920 12.2880 16.3840 24.5760 11.025 11.2896 16.9344 22.5792 33.8688 12 12.2880 18.4320 24.5760 36.8640 sample rate lrck (khz) mclk (mhz) 512x 768x 1024x* 1536x* 16 8.1920 12.2880 16.3840 24.5760 22.05 11.2896 16.9344 22.5792 33.8688 24 12.2880 18.4320 24.5760 36.8640 sample rate lrck (khz) mclk (mhz) 256x 384x 512x* 768x* 32 8.1920 12.2880 16.3840 24.5760 44.1 11.2896 16.9344 22.5792 33.8688 48 12.2880 18.4320 24.5760 36.8640 sample rate lrck (khz) mclk (mhz) 128x 192x 256x* 384x* 64 8.1920 12.2880 16.3840 24.5760 88.2 11.2896 16.9344 22.5792 33.8688 96 12.2880 18.4320 24.5760 36.8640
76 ds679a2 cs42l51 8.2 auto detect disabled sample rate lrck (khz) mclk (mhz) 512x 768x 1024x 1536x 2048x 3072x 8 - 6.1440 8.1920 12.2880 16.3840 24.5760 11.025 - 8.4672 11.2896 16.9344 22.5792 33.8688 12 6.1440 9.2160 12.2880 18.4320 24.5760 36.8640 sample rate lrck (khz) mclk (mhz) 256x 384x 512x 768x 1024x 1536x 16 - 6.1440 8.1920 12.2880 16.3840 24.5760 22.05 - 8.4672 11.2896 16.9344 22.5792 33.8688 24 6.1440 9.2160 12.288 0 18.4320 24.5760 36.8640 sample rate lrck (khz) mclk (mhz) 256x 384x 512x 768x 32 8.1920 12.2880 16.3840 24.5760 44.1 11.2896 16.9344 22.5792 33.8688 48 12.2880 18.4320 24.5760 36.8640 sample rate lrck (khz) mclk (mhz) 128x 192x 256x 384x 64 8.1920 12.2880 16.3840 24.5760 88.2 11.2896 16.9344 22.5792 33.8688 96 12.2880 18.4320 24.5760 36.8640
ds679a2 77 cs42l51 9. pcb layout considerations 9.1 power supply, grounding as with any high resolution converter, the cs42l51 requires careful attention to power supply and grounding arrangements if its potential performance is to be realized. figure 1 on page 10 shows the recommended power arrangements, with va and va_hp connected to clean supplies. vd, which powers the digital circuit- ry, may be run from the system logic supply. alternativ ely, vd may be powered from the analog supply via a ferrite bead. in this case, no additi onal devices should be powered from vd. extensive use of power and ground planes, ground plan e fill in unused areas and surface mount decoupling capacitors are recommended. decoupling capacito rs should be as close to the pins of the cs42l51 as pos- sible. the low value ceramic capacitor should be closest to the pin and should be mounted on the same side of the board as the cs42l51 to minimize inductance effects. all signals, especially clocks, should be kept away from the dac_filt+/adc_ filt+ and vq pins in order to av oid unwanted coupling into the mod- ulators. the dac_filt+/adc_filt+ and vq decoupling capacitors, particularly the 0.1 f, must be posi- tioned to minimize the electrical path from da c_filt+/adc_filt+ and agnd. the cdb42l51 evaluation board demonstrates the optimum layo ut and power supply arrangements. 9.2 qfn thermal pad the cs42l51 is available in a compact qfn package. the under side of the qfn package reveals a large metal pad that serves as a thermal relief to provide fo r maximum heat dissipation. this pad must mate with an equally dimensioned copper pad on the pcb and must be electrically connected to ground. a series of vias should be used to connect this copper pad to one or more larger ground planes on other pcb layers. in split ground systems, it is recommended that th is thermal pad be connected to agnd for best perfor- mance. the cs42l51 evaluation board demonstrates the optimum thermal pad and via configuration.
78 ds679a2 cs42l51 10.adc & dac digital filters -0.3 -0.25 -0.2 -0.15 -0.1 -0.05 0 0.05 0.1 0.15 0.2 0.25 0.3 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 frequency (normalized to fs) amplitude db figure 33. adc passband ripple figure 34. adc stopband rejection -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 frequency (normalized to fs) amplitude db -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.55 frequency (normalized to fs) amplitude db -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 0.4 0.43 0.46 0.49 0.52 0.55 0.58 0.61 0.64 0.67 frequency (normalized to fs) amplitude db figure 35. dac passband ripple figure 36. dac stopband figure 35. dac transition band figure 36. dac tr ansition band (detail) figure 35. adc transition band fi gure 36. adc transition band (detail)
ds679a2 79 cs42l51 11.parameter definitions dynamic range the ratio of the rms value of the signal to the rms su m of all other spectral components over the specified bandwidth. dynamic range is a signal-to-noise ratio measurement over the specified band width made with a -60 dbfs signal. 60 db is added to resulting measurement to refer the measurement to full-scale. this technique ensures that the distortion components are below the noise level and do not affect the measure- ment. this measurement technique has been accept ed by the audio engineer ing society, aes17-1991, and the electronic industries association of japan, eiaj cp-307. expressed in decibels. total harmonic distortion + noise the ratio of the rms value of the signal to the rms su m of all other spectral components over the specified band width (typically 10 hz to 20 kh z), including distortion components. expressed in decibels. measured at -1 and -20 dbfs as suggested in aes17-1991 annex a. frequency response a measure of the amplitude response variation from 10 hz to 20 khz relative to the amplitude response at 1 khz. units in decibels. interchannel isolation a measure of crosstalk between the left and right cha nnel pairs. measured for each channel at the convert- er's output with no signal to the input under test and a full-scale signal applied to the other channel. units in decibels. interchannel gain mismatch the gain difference between left and right channel pairs. units in decibels. gain error the deviation from the nominal full-scale an alog output for a full-scale digital input. gain drift the change in gain value with temperature. units in ppm/c. offset error the deviation of the mid-scale transition (111...111 to 000...000) from the ideal. units in mv.
80 ds679a2 cs42l51 12.package dimensions 1. dimensioning and tolerance per asme y 14.5m-1995. 2. dimensioning lead width applies to the plated te rminal and is measured between 0.20 mm and 0.25 mm from the terminal tip. thermal characteristics inches millimeters note dim min nom max min nom max a----0.0394----1.00 1 a1 0.0000 -- 0.0020 0.00 -- 0.05 1 b 0.0071 0.0091 0.0110 0.18 0.23 0.28 1 , 2 d 0.1969 bsc 5.00 bsc 1 d2 0.1280 0.1299 0.1319 3.25 3.30 3.35 1 e 0.1969 bsc 5.00 bsc 1 e2 0.1280 0.1299 0.1319 3.25 3.30 3.35 1 e 0.0197 bsc 0.50 bsc 1 l 0.0118 0.0157 0.0197 0.30 0.40 0.50 1 jedec #: mo-220 controlling dimension is millimeters. parameter symbol min typ max units junction to ambient thermal impedance 2 layer board 4 layer board ja - - 52 38 - - c/watt side view a1 bottom view top view a pin #1 corner d e d2 l b e pin #1 corner e2 32l qfn (5 x 5 mm body ) package drawing
ds679a2 81 cs42l51 13.ordering information 14.references 1. cirrus logic, audio quality measurement specification , version 1.0, 1997. http://www.cirrus.com/produ cts/papers/meas/meas.html 2. cirrus logic, an18: layout and design rules for data co nverters and other mixed signal devices , version 6.0, february 1998. 3. cirrus logic, techniques to measure and maximize the perf ormance of a 120 db, 96 khz a/d converter integrated circuit , by steven harris, steven green and ka leung . presented at the 103rd convention of the audio engineering society, september 1997. 4. cirrus logic, a stereo 16-bit delta-sigma a/ d converter for digital audio , by d.r. welland, b.p. del signo- re, e.j. swanson, t. tanaka, k. hamashita, s. hara, k. taka suka. paper presented at the 85th convention of the audio engineering society, november 1988. 5. cirrus logic, the effects of sampling clock jitter on nyquis t sampling analog-to-digital converters, and on oversampling delta sigma adc's , by steven harris. paper presented at the 87th convention of the au- dio engineering society, october 1989. 6. cirrus logic, an 18-bit dual-channel oversampling delta-sigm a a/d converter, with 19-bit mono applica- tion example , by clif sanchez. pape r presented at th e 87th convention of the audio engineering society, october 1989. 7. cirrus logic, how to achieve optimum performance fr om delta-sigma a/d and d/a converters , by steven harris. presented at the 93rd convention of the audio engineering society, october 1992. 8. cirrus logic, a fifth-order delta-sigma modulator with 110 db audio dynamic range , by i. fujimori, k. ha- mashita and e.j. swanson. paper pr esented at the 93rd conv ention of the audio engineering society, oc- tober 1992. 9. philips semiconductor, the i2c-bus specification: version 2.1 , january 2000. http://www.semicondu ctors.philips.com product description package pb-free grade temp range container order # cs42l51 low-power stereo codec w/hp amp for portable apps 32l-qfn yes commercial -10 to +70 c rail cs42l51-cnz tape & reel cs42l51-cnzr automotive -40 to +85 c rail CS42L51-DNZ tape & reel CS42L51-DNZr cdb42l51 cs42l51 evaluation board - no - - - cdb42l51 crd42l51 cs42l51 reference design - no - - - crd42l51
82 ds679a2 cs42l51 15.revision history rev. date changes a1 may 2005 initial release subject to legal notice. a2 september 2005 renamed pin 14, filt1+, to dac_filt+ and pin 16, filt2+, to adc_filt+. added 1.5 f capacitor recommendation to figure ?typical connection diagram (software mode)? on page 10 . removed the 0.1f capacitors from pins dac_fi lt+, adc_filt+ and vq on the figures ?typical connection diagram (software mode)? on page 10 and ?typical connection diagram (hardware mode)? on page 11 . added dac isolation specification to ?analog input characterist ics (commercial - cnz)? on page 13 and ?analog input characteristi cs (automotive - dnz)? on page 14 . corrected specification table ?headphone output power characteristics? on page 19 . removed t d timing specification from table in section ?switching specifications - serial port? on page 20 . added t s(sdo-sk) and t h(sk-sdo) timing specification to table in section ?switching specifications - serial port? on page 20 . adjusted timing specifications t s(sd-sk) from 0 ns to 20 ns and t h from 50 ns to 20 ns in table in sec- tion ?switching specifications - serial port? on page 20 . added mic bias psrr specification to ?dc electrical characteristics? on page 24 . adjusted specification table ?power consumption? on page 25 . removed qsm clock ratios 128, 192, 256, 384 and hsm ratios 128, 192 from table 3 on page 37 . modified digital mix description in section ?digital mix (digmix)? on page 50 . corrected dac zero cross timeout period in section ?zero cross? on page 56 . adjusted beep off time settings in section ?beep off time (off time[2:0])? on page 61 . modified beep description in section ?beep (beep)? on page 62 . adjusted the minimum settings for the ?noise gate boost (ng_boost) and threshold (thresh[3:0])? on page 70 . swapped bits pcma_ovfl w/pcmb_ovfl and a dca_ovfl w/adcb_ovfl in register ?status (address 20h) (read only)? on page 71 . corrected charge pump frequency setting in section ?charge pump frequency (chrg_freq[3:0] )? on page 71 . added sections ?headphone thd+n versus output power plots? on page 72 and ?adc_filt+ capacitor effects on thd+n? on page 74 .
ds679a2 83 cs42l51 c ontacting cirrus logic support for all product questions and inquiries cont act a cirrus logic sales representative. t o find the one nearest to you go to www.cirrus.com i mportant notice " advance" product information describes products that are in development and subject to development changes. cirrus logic, inc. and its subsidiaries ("cirrus") believ e t hat the information contained in this document is accurate and reliable. however, the information is subject to change without notice and is provided "as is" withou t w arranty of any kind (express or implied). customers are advised to obtain the latest version of relevant information to verify, before placing orders, that informatio n b eing relied on is current and complete. all products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including thos e p ertaining to warranty, indemnification, and limitation of liabilit y. no responsibility is assumed by cirrus for the use of this information, including use of this informatio n a s the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. this documen t is the property of cirrus and by furnishin g t his information, cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trad e secrets or other intellectual propert y r ights. cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of t he information only for use within you r o rganization with respect to cirrus integrated circuits or other products of cirrus. this consent does not extend to other copyi ng such as copying for general distribution, a dvertising or promotional purposes, or for creating any work for resale. c ertain applications using semiconductor pr oducts may involve potentia l risks of death, personal injury, or severe proper - t y or environmental damage (?critical appl ications?). cirrus products are not design ed, authorized or warranted for use in a ircraft systems, military applications, products surgically impl anted into the body, automotive safety or security devices, l ife support products or other critical applications. inclusion of cirrus products in such applications is understood to b e f ully at the customer?s risk a nd cirrus disclaims and makes no warranty, express, statutory or implied, incl uding the implie d w arranties of merchantability and fitness for particular purpose, with regard to any cirrus product that is used in such a m anner. if the customer or customer?s cu stomer uses or permits the use of cirrus products in critical applications, custom - e r agrees, by such use, to fully indemnify cirrus, its officers, directors, em ployees, distributors an d other agents from an y a nd all liability, including attorneys? fees and costs, that may result from or arise in connection with these uses. c irrus logic, cirrus, and the cirrus logic logo designs are trademarks of cirrus logic, inc. all other brand and product names i n this document may be trademarks o r s ervice marks of their respective owners. s pi is a trademark of motorola, inc.

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